UPD78F1143AGA-HAB-AX Renesas Electronics America, UPD78F1143AGA-HAB-AX Datasheet - Page 489
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UPD78F1143AGA-HAB-AX
Manufacturer Part Number
UPD78F1143AGA-HAB-AX
Description
MCU 16BIT 78K0R/KX3 64-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGA-HAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGA-HAB-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 489 of 880
- Download datasheet (6Mb)
Symbol
IICF0
Address: FFF51H
Note Bits 6 and 7 are read-only.
Cautions 1. Write to STCEN only when the operation is stopped (IICE0 = 0).
Remark
Condition for clearing (IICRSV = 0)
• Cleared by instruction
• Reset
Condition for clearing (STCEN = 0)
• Cleared by instruction
• Detection of start condition
• Reset
Condition for clearing (STCF = 0)
• Cleared by STT0 = 1
• When IICE0 = 0 (operation stop)
• Reset
Condition for clearing (IICBSY = 0)
• Detection of stop condition
• When IICE0 = 0 (operation stop)
• Reset
IICBSY
STCEN
IICRSV
STCF
STCF
<7>
0
1
0
1
0
1
0
1
Generate start condition
Start condition generation unsuccessful: clear STT0 flag
Bus release status (communication initial status when STCEN = 1)
Bus communication status (communication initial status when STCEN = 0)
Enable communication reservation
Disable communication reservation
After operation is enabled (IICE0 = 1), enable generation of a start condition upon detection of
a stop condition.
After operation is enabled (IICE0 = 1), enable generation of a start condition without detecting
a stop condition.
2. As the bus release status (IICBSY = 0) is recognized regardless of the actual bus
3. Write to IICRSV only when the operation is stopped (IICE0 = 0).
STT0: Bit 1 of IIC control register 0 (IICC0)
IICE0: Bit 7 of IIC control register 0 (IICC0)
IICBSY
<6>
After reset: 00H
status when STCEN = 1, when generating the first start condition (STT0 = 1), it is
necessary to verify that no third party communications are in progress in order to
prevent such communications from being destroyed.
Figure 12-8. Format of IIC Flag Register 0 (IICF0)
5
0
CHAPTER 12 SERIAL INTERFACE IIC0
User’s Manual U17854EJ9V0UD
R/W
Communication reservation function disable bit
4
0
Note
3
0
Initial start enable trigger
I
2
STT0 clear flag
C bus status flag
Condition for setting (IICRSV = 1)
• Set by instruction
Condition for setting (STCF = 1)
• Generating start condition unsuccessful and STT0
Condition for setting (IICBSY = 1)
• Detection of start condition
• Setting of IICE0 when STCEN = 0
Condition for setting (STCEN = 1)
• Set by instruction
2
0
cleared to 0 when communication reservation is
disabled (IICRSV = 1).
STCEN
<1>
IICRSV
<0>
487
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