UPD78F1143AGA-HAB-AX Renesas Electronics America, UPD78F1143AGA-HAB-AX Datasheet - Page 556
UPD78F1143AGA-HAB-AX
Manufacturer Part Number
UPD78F1143AGA-HAB-AX
Description
MCU 16BIT 78K0R/KX3 64-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGA-HAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
UPD78F1143AGA-HAB-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Address: FFFBAH (DMC0), FFFBBH (DMC1)
Symbol
DMCn
(1) DMA mode control register n (DMCn)
DMCn is a register that is used to set a transfer mode of DMA channel n. It is used to select a transfer
direction, data size, setting of pending, and start source. Bit 7 (STGn) is a software trigger that starts DMA.
Rewriting bits 6, 5, and 3 to 0 of DMCn is prohibited during operation (when DSTn = 1).
DMCn can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Notes 1. The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 values.
Remark
DMA transfer is performed once by writing 1 to STGn when DMA operation is enabled (DENn = 1).
When this bit is read, 0 is always read.
DMA transfer that has been held pending can be started by clearing the value of DWAITn to 0.
It takes 2 clocks to actually hold DMA transfer pending when the value of DWAITn is set to 1.
DWAITn
STGn
2. When DMA transfer is held pending while using both DMA channels, be sure to hold the DMA
DRSn
STGn
DSn
<7>
transfer pending for both channels (by setting DWAIT0 and DWAIT1 to 1).
0
1
0
1
0
1
0
1
n: DMA channel number (n = 0, 1)
Note 1
Note 2
Figure 14-4. Format of DMA Mode Control Register n (DMCn) (1/2)
No trigger operation
DMA transfer is started when DMA operation is enabled (DENn = 1).
SFR to internal RAM
Internal RAM to SFR
8 bits
16 bits
Executes DMA transfer upon DMA start request (not held pending).
Holds DMA start request pending if any.
DRSn
<6>
CHAPTER 14 DMA CONTROLLER
After reset: 00H
DSn
<5>
User’s Manual U17854EJ9V0UD
Specification of transfer data size for DMA transfer
DWAITn
Selection of DMA transfer direction
DMA transfer start software trigger
<4>
R/W
Pending of DMA transfer
IFCn3
3
IFCn2
2
IFCn1
1
IFCn0
0
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