UPD78F1143AGA-HAB-AX Renesas Electronics America, UPD78F1143AGA-HAB-AX Datasheet - Page 494
UPD78F1143AGA-HAB-AX
Manufacturer Part Number
UPD78F1143AGA-HAB-AX
Description
MCU 16BIT 78K0R/KX3 64-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGA-HAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGA-HAB-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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12.5 I
Figure 12-13 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the
I
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device
that receives 8-bit data).
level period can be extended and a wait can be inserted.
12.5.1 Start conditions
The start conditions for the SCL0 pin and SDA0 pin are signals that the master device generates to the slave device
when starting a serial transfer. When the device is used as a slave, start conditions can be detected.
been detected (SPD0: Bit 0 = 1 in IIC status register 0 (IICS0)). When a start condition is detected, bit 1 (STD0) of
IICS0 is set (to 1).
492
2
C bus’s serial data bus.
The following section describes the I
The master device generates the start condition, slave address, and stop condition.
The serial clock (SCL0) is continuously output by the master device. However, in the slave device, the SCL0’s low
A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level.
A start condition is output when bit 1 (STT0) of IIC control register 0 (IICC0) is set (to 1) after a stop condition has
2
C Bus Definitions and Control Methods
SDA0
SCL0
Start
condition
Figure 12-13. I
Address R/W ACK
1-7
SDA0
SCL0
CHAPTER 12 SERIAL INTERFACE IIC0
2
C bus’s serial data communication format and the signals used by the I
Figure 12-14. Start Conditions
8
H
User’s Manual U17854EJ9V0UD
2
C Bus Serial Data Transfer Timing
9
Data
1-8
ACK
9
Data
1-8
ACK
9
Stop
condition
2
C bus.
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