UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 211
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UPD78F1146AGB-GAH-AX
Manufacturer Part Number
UPD78F1146AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1146AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1146AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.4 Channel Output (TO0n pin) Control
6.4.1 TO0n pin output circuit configuration
Interrupt signal of the master channel
Interrupt signal of the slave channel
The following describes the TO0n pin output circuit.
<1> When TOM0n = 0 (toggle mode), the set value of the TOL0n register is ignored and only INTTM0p (slave
<2> When TOM0n = 1 (combination-operation mode), both INTTM0n (master channel timer interrupt) and
<3> When TOE0n = 1, INTTM0n (master channel timer interrupt) and INTTM0p (slave channel timer interrupt)
<4> When TOE0n = 0, writing to TO0n bit to the target channel (TO0n write signal) becomes valid. When
<5> The TO0n register can always be read, and the TO0n pin output level can be checked.
Remarks 1. n = 0 to 6 (n = 0, 2, or 4 for master channel)
channel timer interrupt) is transmitted to the TO0n register.
INTTM0p (slave channel timer interrupt) are transmitted to the TO0n register.
At this time, the TOL0n register becomes valid and the signals are controlled as follows:
When INTTM0n and INTTM0p are simultaneously generated, (0% output of PWM), INTTM0p (reset
signal) takes priority, and INTTM0n (set signal) is masked.
are transmitted to the TO0n register. Writing to the TO0n register (TO0n write signal) becomes invalid.
When TOE0n = 1, the TO0n pin output never changes with signals other than interrupt signals.
To initialize the TO0n pin output level, it is necessary to set TOE0n = 0 and to write a value to TO0n.
TOE0n = 0, neither INTTM0n (master channel timer interrupt) nor INTTM0p (slave channel timer
interrupt) is transmitted to TO0n register.
When TOL0n = 0: Forward operation (INTTM0 → set, INTTM0p → reset)
When TOL0n = 1: Reverse operation (INTTM0 → reset, INTTM0p → set)
2. p = n + 1, n + 2, n + 3 ... (where p ≤ 6)
(INTTM0n)
(INTTM0p)
Figure 6-24. Output Circuit Configuration
CHAPTER 6 TIMER ARRAY UNIT
User’s Manual U17854EJ9V0UD
<1>
<2>
TOL0n
TOM0n
TOE0n
<3>
TO0n write signal
<4>
TO0n register
Set
Reset/toggle
<5>
Internal bus
TO0n pin
209
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