UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 585
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UPD78F1146AGB-GAH-AX
Manufacturer Part Number
UPD78F1146AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1146AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1146AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon reset signal generation.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt
routine is entered.
IF0L, IF0H, IF1L, IF1H, IF2L, and IF2H can be set by a 1-bit or 8-bit memory manipulation instruction. When
IF0L and IF0H, IF1L and IF1H, and IF2L and IF2H are combined to form 16-bit registers IF0, IF1, and IF2, they
can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
Address: FFFE0H After reset: 00H R/W
Address: FFFE1H
Address: FFFE2H
Address: FFFE3H
Address: FFFD0H
Address: FFFD1H
Symbol
Symbol
Symbol
Symbol
Symbol
Symbol
IF0H
IF1H
IF2H
IF0L
IF1L
IF2L
Figure 15-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)
increases by 2 clocks.
SREIF0
TMIF03
TMIF04
XXIFX
PIF10
PIF5
<7>
<7>
<7>
<7>
<7>
7
0
0
1
After reset: 00H
After reset: 00H
After reset: 00H
After reset: 00H
After reset: 00H
No interrupt request signal is generated
Interrupt request is generated, interrupt request status
TMIF02
SRIF0
PIF4
PIF9
<6>
<6>
<6>
<6>
6
0
6
0
CHAPTER 15 INTERRUPT FUNCTIONS
R/W
R/W
R/W
R/W
R/W
CSIIF00
TMIF01
STIF0
PIF3
PIF8
<5>
<5>
<5>
<5>
User’s Manual U17854EJ9V0UD
5
0
5
0
DMAIF1
TMIF00
PIF2
PIF7
<4>
<4>
<4>
<4>
4
0
4
0
Interrupt request flag
DMAIF0
IICIF0
KRIF
PIF1
PIF6
<3>
<3>
<3>
<3>
<3>
3
0
SREIF3
SREIF1
TMIF07
RTCIIF
PIF0
<2>
<2>
<2>
<2>
<2>
2
0
TMIF06
SRIF3
RTCIF
SRIF1
LVIIF
<1>
<1>
<1>
<1>
<1>
1
0
CSIIF10
WDTIIF
TMIF05
IICIF10
STIF3
STIF1
PIF11
ADIF
<0>
<0>
<0>
<0>
<0>
<0>
583
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