UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 422
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UPD78F1146AGB-GAH-AX
Manufacturer Part Number
UPD78F1146AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1146AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1146AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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11.6.1 UART transmission
stop synchronization).
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
420
Remarks 1. f
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
UART transmission is an operation to transmit data from the 78K0R/KE3 to another device asynchronously (start-
Of two channels used for UART, the even channel is used for UART transmission.
specifications (see CHAPTER 27
CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
UART
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 12
f
MCK
CLK
: System clock frequency
: Operation clock (MCK) frequency of target channel
TxD0
Channel 0 of SAU0
INTST0
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
None
5, 7, or 8 bits
Max. f
Forward output (default: high level)
Reverse output (default: low level)
The following selectable
• No parity bit
• Appending 0 parity
• Appending even parity
• Appending odd parity
The following selectable
• Appending 1 bit
• Appending 2 bits
MSB or LSB first
MCK
/6 [bps] (SDRmn [15:9] = 2 or more), Min. f
UART0
CHAPTER 11 SERIAL ARRAY UNIT
User’s Manual U17854EJ9V0UD
ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and
Channel 2 of SAU0
TxD1
INTST1
UART1
CLK
/(2 × 2
11
× 128) [bps]
Channel 2 of SAU1
TxD3
INTST3
Note
UART3
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