UPD78F1146AGB-GAH-AX Renesas Electronics America, UPD78F1146AGB-GAH-AX Datasheet - Page 427
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UPD78F1146AGB-GAH-AX
Manufacturer Part Number
UPD78F1146AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1146AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1146AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Figure 11-74. Procedure for Resuming UART Transmission
Changing setting of SDRm register
Changing setting of SOEm register
Changing setting of SOEm register
Changing setting of SPSm register
Changing setting of SMRmn register
Changing setting of SCRmn register
Changing setting of SOLmn register
Changing setting of SOm register
Starting setting for resumption
Starting communication
Writing to SSm register
Port manipulation
Port manipulation
CHAPTER 11 SERIAL ARRAY UNIT
User’s Manual U17854EJ9V0UD
Enable data output of the target channel
by setting a port register and a port mode
register.
SEmn = 1 when the SSmn bit of the
target channel is set to 1.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if an incorrect
transfer baud rate is set.
Change the setting if the setting of the
SMRmn register is incorrect.
Change the setting if the setting of the
SCRmn register is incorrect.
Change the setting if the setting of the
SOLmn register is incorrect.
Manipulate the SOmn bit and set an
initial output level.
Sets transmit data to the TXDq register
(bits 7 to 0 of the SDRmn register) and
start communication.
Set the SOEmn bit to 1 and enable
output.
Disable data output of the target channel
by setting a port register and a port mode
register.
Clear the SOEmn bit to 0 and stop
output.
425
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