UPD70F3743GJ-GAE-AX Renesas Electronics America, UPD70F3743GJ-GAE-AX Datasheet - Page 586

• Manufacturer Part Number: UPD70F3743GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3743GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
IICX0
CLX0
Bit 0
Note Since the selection clock is f
Remark
0
0
0
0
0
0
0
1
1
Other than above
SMC0
Bit 3
00H (I
0
0
0
0
1
1
1
1
1
×: don't care
IICCL0
2
CL01
C division clock stopped status).
Bit 1
0
0
1
1
0
1
1
0
1
CL00
Bit 0
0
1
0
1
×
0
1
×
0
Setting prohibited
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
/2 (when OCKS0 = 10H set)
/3 (when OCKS0 = 11H set)
/4 (when OCKS0 = 12H set)
/5 (when OCKS0 = 13H set)
/2 (when OCKS0 = 10H set)
/3 (when OCKS0 = 11H set)
/4 (when OCKS0 = 12H set)
/5 (when OCKS0 = 13H set)
Note
/2 (when OCKS0 = 10H set)
/3 (when OCKS0 = 11H set)
/4 (when OCKS0 = 12H set)
/5 (when OCKS0 = 13H set)
/2 (when OCKS0 = 10H set)
/3 (when OCKS0 = 11H set)
/4 (when OCKS0 = 12H set)
Note
/2 (when OCKS0 = 10H set)
/3 (when OCKS0 = 11H set)
/4 (when OCKS0 = 12H set)
/5 (when OCKS0 = 13H set)
/2 (when OCKS0 = 10H set)
/3 (when OCKS0 = 11H set)
/4 (when OCKS0 = 12H set)
/5 (when OCKS0 = 13H set)
Note
(when OCKS0 = 18H set)
(when OCKS0 = 18H set)
(when OCKS0 = 18H set)
(when OCKS0 = 18H set)
(when OCKS0 = 18H set)
(when OCKS0 = 18H set)
XX
Selection Clock
regardless of the value set to the OCKS0 register, clear the OCKS0 register to
Table 17-2. Clock Settings (1/2)
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
Transfer
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
Clock
/44
/88
/132
/176
/220
/86
/172
/258
/344
/430
/86
/66
/132
/198
/264
/330
/24
/48
/72
/96
/24
/18
/36
/54
/72
/90
/12
/24
/36
/48
/60
/12
−
2.00 MHz ≤ f
4.00 MHz ≤ f
6.00 MHz ≤ f
8.00 MHz ≤ f
10.00 MHz ≤ f
4.19 MHz ≤ f
8.38 MHz ≤ f
12.57 MHz ≤ f
16.76 MHz ≤ f
20.95 MHz ≤ f
4.19 MHz ≤ f
6.40 MHz
12.80 MHz
19.20 MHz
25.60 MHz
32.00 MHz
4.19 MHz ≤ f
8.00 MHz ≤ f
12.00 MHz ≤ f
16.00 MHz ≤ f
4.00 MHz ≤ f
6.40 MHz
12.80 MHz
19.20 MHz
25.60 MHz
32.00 MHz
4.00 MHz ≤ f
8.00 MHz ≤ f
12.00 MHz ≤ f
16.00 MHz ≤ f
20.00 MHz ≤ f
4.00 MHz ≤ f
Frequency (f
Settable Main Clock
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
−
≤ 4.19 MHz
≤ 8.38 MHz
≤ 12.57 MHz
≤ 16.76 MHz
≤ 8.38 MHz
≤ 16.76 MHz
≤ 8.38 MHz
≤ 8.38 MHz
≤ 16.76 MHz
≤ 8.38 MHz
≤ 4.19 MHz
≤ 8.38 MHz
≤ 4.19 MHz
XX
≤ 20.95 MHz
≤ 25.14 MHz
≤ 32.00 MHz
≤ 32.00 MHz
≤ 25.14 MHz
≤ 32.00 MHz
≤ 12.57 MHz
≤ 16.67 MHz
≤ 20.95 MHz
) Range
CHAPTER 17 I
Standard mode
(SMC0 bit = 0)
High-speed
mode
(SMC0 bit = 1)
Operating
Page 570 of 892
Mode
−
2
C BUS