UPD70F3743GJ-GAE-AX Renesas Electronics America, UPD70F3743GJ-GAE-AX Datasheet - Page 876

• Manufacturer Part Number: UPD70F3743GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3743GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
Bus
control
functions
Clock
generation
function
Function
DWC0 register
AWC register
BCC register
PCC register
RCM register
PLLCTL
register
CKC register
Details of
Function
Write to the DWC0 register after reset, and then do not change the set values.
Also, do not access an external memory area until the initial settings of the DWC0
register are complete.
When V850ES/JJ3 is used in separate bus mode and operated at f
be sure to insert one or more wait.
Be sure to clear bits 15, 11, 7, and 3 to “0”.
Address setup wait and address hold wait cycles are not inserted when the
internal ROM area, internal RAM area, and on-chip peripheral I/O areas are
accessed.
Write to the AWC register after reset, and then do not change the set values.
Also, do not access an external memory area until the initial settings of the AWC
register are complete.
When V850ES/JJ3 is operated at f
wait and the address setup wait.
Be sure to set bits 15 to 8 to “1”.
The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject
to idle state insertion.
Write to the BCC register after reset, and then do not change the set values. Also,
do not access an external memory area until the initial settings of the BCC
register are complete.
Be sure to set bits 15, 13, 11, and 9 to “1”, and clear bits 14, 12, 10, 8, 6, 4, 2,
and 0 to “0”.
Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is
being output.
Use a bit manipulation instruction to manipulate the CK3 bit. When using an 8-bit
manipulation instruction, do not change the set values of the CK2 to CK0 bits.
When stopping the main clock, stop the PLL. Also stop the operations of the on-
chip peripheral functions operating with the main clock.
If the following conditions are not satisfied, change the CK2 to CK0 bits so that
the conditions are satisfied, then change to the subclock operation mode.
Internal system clock (f
Enable operation of the on-chip peripheral functions operating with the main clock
only after the oscillation of the main clock stabilizes. If their operations are
enabled before the lapse of the oscillation stabilization time, a malfunction may
occur.
The internal oscillator cannot be stopped while the CPU is operating on the
internal oscillation clock (CCLS.CCLSF bit = 1). Do not set the RSTOP bit to 1.
The internal oscillator oscillates if the CCLS.CCLSF bit is set to 1 (when WDT
overflow occurs during oscillation stabilization) even when the RSTOP bit is set to
1. At this time, the RSTOP bit remains being set to 1.
When the PLLON bit is cleared to 0, the SELPLL bit is automatically cleared to 0
(clockthrough mode).
The SELPLL bit can be set to 1 only when the PLL clock frequency is stabilized. If
not (unlocked), “0” is written to the SELPLL bit if data is written to it.
The PLL mode cannot be used at f
Before changing the multiplication factor between 4 and 8 by using the CKC
register, set the clock-through mode and stop the PLL.
Be sure to set bits 3 and 1 to “1” and clear bits 7 to 4 and 2 to “0”.
CLK
) > Subclock (f
XX
X
= 5.0 to 10.0 MHz.
Cautions
> 20 MHz, be sure to insert the address hold
XT
: 32.768 kHz) × 4
APPENDIX E LIST OF CAUTIONS
XX
> 20 MHz,
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