UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 1180
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UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
23.2 Non-Maskable Interrupts
disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupt request
signals.
detection”.
WDTM2.WDM21 and WDTM2.WDM20 bits are set to “01”.
serviced, as follows (the interrupt request signal with the lower priority is ignored).
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
A non-maskable interrupt request signal is acknowledged unconditionally, even when interrupts are in the interrupt
This product has the following two non-maskable interrupt request signals.
• NMI pin input (NMI)
• Non-maskable interrupt request signal generated by overflow of watchdog timer (INTWDT2)
The valid edge of the NMI pin can be selected from four types: “rising edge”, “falling edge”, “both edges”, and “no edge
The non-maskable interrupt request signal generated by overflow of watchdog timer 2 (INTWDT2) functions when the
If two or more non-maskable interrupt request signals occur at the same time, the interrupt with the higher priority is
INTWDT2 > NMI
If a new NMI or INTWDT2 request signal is issued while an NMI is being serviced, it is serviced as follows.
(1) If new NMI request signal is issued while NMI is being serviced
(2) If INTWDT2 request signal is issued while NMI is being serviced
The new NMI request signal is held pending, regardless of the value of the PSW.NP bit. The pending NMI request
signal is acknowledged after the NMI currently under execution has been serviced (after the RETI instruction has
been executed).
The INTWDT2 request signal is held pending if the NP bit remains set (1) while the NMI is being serviced. The
pending INTWDT2 request signal is acknowledged after the NMI currently under execution has been serviced (after
the RETI instruction has been executed).
If the NP bit is cleared (0) while the NMI is being serviced, the newly generated INTWDT2 request signal is
executed (the NMI servicing is stopped).
Caution For the non-maskable interrupt servicing executed by the non-maskable interrupt request signal
Figure 23-1. Non-Maskable Interrupt Request Signal Acknowledgment Operation (1/2)
(INTWDT2), see 23.2.2 (2) From INTWDT2 signal.
(a) NMI and INTWDT2 request signals generated at the same time
NMI and
(generated simultaneously)
INTWDT2 requests
CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Main routine
System reset
INTWDT2 servicing
Page 1180 of 1408
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