PIC17LC756AT-08/L Microchip Technology, PIC17LC756AT-08/L Datasheet - Page 151
![IC MCU OTP 16KX16 A/D 68PLCC](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC17LC756AT-08/L
Manufacturer Part Number
PIC17LC756AT-08/L
Description
IC MCU OTP 16KX16 A/D 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Specifications of PIC17LC756AT-08/L
Core Processor
PIC
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Processor Series
PIC17LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
902 B
Interface Type
I2C, MSSP, RS- 232, SCI, SPI, USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
50
Number Of Timers
8
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
12 bit
Data Rom Size
902 B
Height
4.06 mm
Length
24.33 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
3 V
Width
24.33 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17LC756AT-08/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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15.2.5
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET, or when the MSSP module is
disabled. Control of the I
P bit is set, or the bus is idle, with both the S and P bits
clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
FIGURE 15-17:
2000 Microchip Technology Inc.
SDA
SCL
MASTER MODE
SSP BLOCK DIAGRAM (I
2
C bus may be taken when the
SDA In
Bus Collision
SCL In
Read
Write Collision Detect
MSb
START bit, STOP bit,
START bit Detect,
end of XMIT/RCV
State Counter for
Clock Arbitration
STOP bit Detect
Acknowledge
SSPBUF
Generate
SSPSR
2
C MASTER MODE)
LSb
Write
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
Clock
Data Bus
Shift
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
PIC17C7XX
SSPADD<6:0>
SSPM3:SSPM0
Baud
Rate
Generator
DS30289B-page 151
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