PIC17LC756AT-08/L Microchip Technology, PIC17LC756AT-08/L Datasheet - Page 257
![IC MCU OTP 16KX16 A/D 68PLCC](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC17LC756AT-08/L
Manufacturer Part Number
PIC17LC756AT-08/L
Description
IC MCU OTP 16KX16 A/D 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Specifications of PIC17LC756AT-08/L
Core Processor
PIC
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Processor Series
PIC17LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
902 B
Interface Type
I2C, MSSP, RS- 232, SCI, SPI, USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
50
Number Of Timers
8
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
12 bit
Data Rom Size
902 B
Height
4.06 mm
Length
24.33 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
3 V
Width
24.33 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17LC756AT-08/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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FIGURE 20-16:
TABLE 20-11: SPI MODE REQUIREMENTS (SLAVE MODE, CKE = 1)
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
Param.
2000 Microchip Technology Inc.
71A
72A
73A
No.
†
70
71
72
74
75
76
77
80
82
83
(CKP = 0)
(CKP = 1)
SDI
SDI
SS
SCK
SCK
SDO
TssL2scH,
TssL2scL
TscH
TscL
T
TscH2diL,
TscL2diL
TdoR
TdoF
TssH2doZ
TscH2doV,
TscL2doV
TssL2doV
TscH2ssH,
TscL2ssH
Data in "Typ" column is at 5V, 25°C unless otherwise stated.
B
Symbol
2
B
82
SPI SLAVE MODE TIMING (CKE = 1)
Note:
SS to SCK or SCK input
SCK input high time
(Slave mode)
SCK input low time
(Slave mode)
Last clock edge of Byte1 to the 1st clock edge
of Byte2
Hold time of SDI data input to SCK edge
SDO data output rise time
SDO data output fall time
SS to SDO output hi-impedance
SDO data output valid after SCK edge
SDO data output valid after SS edge
SS
70
after SCK edge
MSb IN
MSb
Refer to Figure 20-5 for load conditions.
74
71
Characteristic
75, 76
72
BIT6 - - - - - -1
BIT6 - - - -1
Continuous
Single Byte
Continuous
Single Byte
80
1.25T
1.25T
1.5T
1.5T
LSb
LSb IN
Min
100
Tcy
CY
CY
40
40
10
CY
CY
—
—
—
—
+ 40
+ 40
+ 30
+ 30
Typ†
—
—
—
—
—
—
—
10
10
—
—
—
—
83
PIC17C7XX
Max
25
25
50
50
50
—
—
—
—
—
—
—
—
77
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS30289B-page 257
(Note 1)
(Note 1)
(Note 1)
Conditions
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