PIC17LC756AT-08/L Microchip Technology, PIC17LC756AT-08/L Datasheet - Page 224
![IC MCU OTP 16KX16 A/D 68PLCC](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC17LC756AT-08/L
Manufacturer Part Number
PIC17LC756AT-08/L
Description
IC MCU OTP 16KX16 A/D 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Specifications of PIC17LC756AT-08/L
Core Processor
PIC
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Processor Series
PIC17LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
902 B
Interface Type
I2C, MSSP, RS- 232, SCI, SPI, USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
50
Number Of Timers
8
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
12 bit
Data Rom Size
902 B
Height
4.06 mm
Length
24.33 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
3 V
Width
24.33 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17LC756AT-08/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC17C7XX
RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example 1:
Example 2:
DS30289B-page 224
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
WREG
REG
WREG
REG
WREG
REG
WREG
REG
Q1
=
=
=
=
=
=
=
=
register ’f’
Rotate Right f (no carry)
[ label ]
0
d
f<n>
f<0>
None
The contents of register ’f’ are rotated
one bit to the right. If ’d’ is 0, the result is
placed in WREG. If ’d’ is 1, the result is
placed back in register ’f’.
1
1
RRNCF
RRNCF
Read
0010
Q2
?
1101 0111
0
1110 1011
?
1101 0111
1110 1011
1101 0111
f
[0,1]
255
d<n-1>;
d<7>
REG, 1
REG, 0
RRNCF f,d
000d
Process
Data
Q3
register f
ffff
destination
Write to
Q4
ffff
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example1:
Example2:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
WREG
REG
WREG
REG
WREG
REG
WREG
Q1
=
=
=
=
=
=
=
=
register ’f’
SETF
Set f
[ label ]
0
s
FFh
FFh
None
If ’s’ is 0, both the data memory location
’f’ and WREG are set to FFh. If ’s’ is 1,
only the data memory location ’f’ is set
to FFh.
1
1
SETF
Read
0010
Q2
0xDA
0x05
0xFF
0xFF
0xDA
0x05
0xFF
0x05
f
[0,1]
2000 Microchip Technology Inc.
255
f;
d
REG, 1
REG, 0
SETF f,s
101s
Process
Data
Q3
ffff
register ’f’
and other
specified
register
Write
Q4
ffff
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