ATMEGA163-8AI Atmel, ATMEGA163-8AI Datasheet
ATMEGA163-8AI
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ATMEGA163-8AI Summary of contents
Page 1
... PDIP and 44-pin TQFP • Operating Voltages – 2.7 - 5.5V for ATmega163L – 4.0 - 5.5V for ATmega163 • Speed Grades – MHz for ATmega163L – MHz for ATmega163 ® 8-bit Microcontroller 8-bit Microcontroller with 16K Bytes In-System Programmable Flash ...
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... Pin Configurations ATmega163(L) 2 (SDA) (SCL) 1142E–AVR–02/03 ...
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... Description The ATmega163 is a low-power CMOS 8-bit microcontroller based on the AVR architec- ture. By executing powerful instructions in a single clock cycle, the ATmega163 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 1. Block Diagram The AVR core combines a rich instruction set with 32 general purpose working registers ...
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... Atmel ATmega163 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega163 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Cir- cuit Emulators, and evaluation kits. ...
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... Port C also serves the functions of various special features of the ATmega163 as listed on page 124. Port D (PD7..PD0) Port 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated ...
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... Timer Oscillator For the Timer Oscillator pins, TOSC1 and TOSC2, the crystal is connected directly between the pins. No external capacitors are needed. The Oscillator is optimized for use with a 32,768 Hz watch crystal. Applying an external clock source to the TOSC1 pin is not recommended. ATmega163( XTAL2 ...
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... The ALU supports arithmetic and logic operations between registers or between a con- stant and a register. Single register operations are also executed in the ALU. Figure 5 shows the ATmega163 AVR Enhanced RISC microcontroller architecture. In addition to the register operation, the conventional Memory Addressing modes can be used on the Register File as well ...
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... Figure 5. The ATmega163 AVR RISC Architecture The AVR uses a Harvard architecture concept – with separate memories and buses for program and data. The Program memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the Program memory ...
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... Vector in the Interrupt Vector table at the beginning of the Program memory. The inter- rupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. Figure 6. Memory Maps 1142E–AVR–02/03 ATmega163(L) Program Memory $0000 Application Flash Section Boot Flash Section ...
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... The registers R26..R31 have some added functions to their general purpose usage. Z-register These registers are address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as: Figure 8. The X-, Y-, and Z-registers ATmega163( General Purpose ...
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... Boot Program section and Application Program section. The Flash memory has an endurance of at least 1,000 write/erase cycles. The ATmega163 Program Counter (PC bits wide, thus addressing the 8,192 Program Memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail on page 134. See also page 154 for a detailed description on Flash data serial downloading ...
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... When using register indirect addressing modes with automatic pre-decrement and post- increment, the address registers X, Y, and Z are decremented and incremented. The 32 general purpose working registers, 64 I/O Registers, and the 1,024 bytes of internal data SRAM in the ATmega163 are all accessible through all these addressing modes. The Program and Data ...
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... Operand address is contained in 6 bits of the instruction word the destination or source register address. Data Direct Figure 13. Direct Data Addressing A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. 1142E–AVR–02/ Rr/Rd 16 LSBs 15 0 ATmega163(L) Data Space $0000 $045F 13 ...
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... Figure 15. Data Indirect Addressing Operand address is the contents of the X-, Y-, or the Z-register. Data Indirect with Pre- Figure 16. Data Indirect Addressing with Pre-decrement decrement The X-, Y-, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or the Z-register. ATmega163( REGISTER 15 10 ...
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... For SPM, the LSB should be cleared. Indirect Program Addressing, Figure 19. Indirect Program Memory Addressing IJMP and ICALL Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register). 1142E–AVR–02/ REGISTER 1 ATmega163(L) Data Space $0000 $045F $1FFF $1FFF 15 ...
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... Program execution continues at address The relative address k is from -2,048 to 2,047. The EEPROM Data The ATmega163 contains 512 bytes of data EEPROM memory organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an Memory endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 62 specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
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... Figure 22. Single Cycle ALU Operation The internal data SRAM access is performed in two System Clock cycles as described in Figure 23. Figure 23. On-chip Data SRAM Access Cycles I/O Memory The I/O space definition of the ATmega163 is shown in the following table: Table 2. ATmega163 I/O Space 1142E–AVR–02/03 T1 System Clock Ø ...
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... Table 2. ATmega163 I/O Space (Continued) ATmega163(L) 18 I/O Address (SRAM Address) Name Function $32 ($52) TCNT0 Timer/Counter0 (8-bit) $31 ($51) OSCCAL Oscillator Calibration Register $30 ($50) SFIOR Special Function I/O Register $2F ($4F) TCCR1A Timer/Counter1 Control Register A $2E ($4E) TCCR1B Timer/Counter1 Control Register B $2D ($4D) TCNT1H Timer/Counter1 High-byte ...
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... Table 2. ATmega163 I/O Space (Continued) Note: All ATmega163 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general pur- pose working registers and the I/O space. I/O Registers within the address range $00 - the value of single bits can be checked by using the SBIS and SBIC instructions ...
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... The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the Status Register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine. This must be handled by software. ATmega163(L) 20 Bit 7 6 ...
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... The Stack Pointer – SP The ATmega163 Stack Pointer is implemented as two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the ATmega163 data memory has $460 loca- tions, 11 bits are used. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Inter- rupt Stacks are located ...
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... Table 3. Reset and Interrupt Vectors (Continued) Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega163 is: ATmega163(L) 22 Program Vector No. Address Source 13 $018 UART, UDRE 14 $01A UART, TXC 15 $01C ADC 16 $01E EE_RDY 17 $020 ANA_COMP 18 $022 TWI 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see “ ...
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... When the BOOTRST Fuse is programmed and the Boot section size set to 512 bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega163 is: Reset Sources The ATmega163 has four sources of reset: • • • • During Reset, all I/O Registers are set to their initial values, and the program starts exe- cution from address $000 (unless the BOOTRST Fuse is programmed, as explained above). The instruction placed in this address location must be a JMP – ...
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... Figure 24. Reset Logic Table 4. Reset Characteristics (V Notes: ATmega163(L) 24 Power-on VCC Reset Circuit Brown-out BODEN Reset Circuit BODLEVEL 100-500kW SPIKE RESET Reset Circuit FILTER Watchdog Timer On-chip RC Oscillator Clock Generator CKSEL[3:0] CC Symbol Parameter V Power-on Reset Threshold POT Voltage (rising) Power-on Reset Threshold ...
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... On power-up, the start-up time is increased with typ. 0.6 ms. 2. “1” means unprogrammed, “0” means programmed. 3. For possible clock selections, see “Clock Options” on page 5. 4. When BODEN is programmed, add 100 µs. 5. When BODEN is programmed, add 25 µs. 6. Default value. ATmega163(L) = 4.0V, CC Recommended Usage Ext. Clock, fast rising power (5) Ext ...
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... RESET after V the delay counter can be defined by the user through the CKSEL Fuses. The different selections for the delay period are presented in Table 5. The RESET signal is activated again, without any delay, when the V Figure 25. MCU Start-up, RESET Tied to V ATmega163(L) 26 BODLEVEL V Condition ...
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... Time-out Period t Figure 27. External Reset During Operation Brown-out Detection ATmega163 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is enabled (BODEN programmed), and V value below the trigger level, the Brown-out Reset is immediately activated. When V increases above the trigger level, the Brown-out Reset is deactivated after a delay ...
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... MCUSR Reset. • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega163 and always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the Flag. ...
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... Reset Flags. Internal Voltage Reference ATmega163 features an internal bandgap reference with a nominal voltage of 1.22V. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator and ADC. The 2.56V reference to the ADC is also generated from the internal bandgap reference ...
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... INT0 is configured as an output. The corre- sponding interrupt of External Interrupt Request 0 is executed from Program Memory address $002. See also “External Interrupts.” • Bits 5 – Res: Reserved Bits This bit is reserved in the ATmega163 and the read value is undefined. ATmega163(L) 30 Bit ...
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... Bits 4..0 – Res: Reserved Bits These bits are reserved bits in the ATmega163 and always read as zero. The General Interrupt Flag Register – GIFR • Bit 7 – INTF1: External Interrupt Flag1 When an edge on the INT1 pin triggers an interrupt request, the correspnding Interrupt Flag, INTF1, becomes set (one) ...
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... Timer/Counter Interrupt Flag Register – TIFR. • Bit 1 – Res: Reserved Bit This bit is a reserved bit in the ATmega163 and always reads as zero. • Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow Interrupt is enabled ...
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... Timer/Counter1 changes counting direction at $0000. • Bit 1 – Res: Reserved Bit This bit is a reserved bit in the ATmega163 and the read value is undefined. • Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding Interrupt Handling Vector ...
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... The MCU Control Register contains control bits for general MCU functions. MCUCR • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATmega163 and always reads as zero. • Bit 6 – SE: Sleep Enable The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed ...
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... Timer/Counter2 interrupts during ADC Noise Reduction mode if the Timer/Counter2 is clocked synchronously. 1142E–AVR–02/03 ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request Any logical change on INT0 generates an interrupt request The falling edge of INT0 generates an interrupt request The rising edge of INT0 generates an interrupt request. ATmega163(L) 35 ...
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... Timer/Counter2 interrupt enable bits are set in TIMSK, and the global interrupt enable bit in SREG is set. If the asynchronous timer is NOT clocked asynchronously, Power-down mode is recom- mended instead of Power-save mode because the contents of the registers in the asynchronous timer should be considered undefined after wake-up in Power-save mode if AS2 is 0. ATmega163(L) 36 1142E–AVR–02/03 ...
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... SFIOR • Bit 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega163 and always read as zero. • Bit 3 – ACME: Analog Comparator Multiplexer Enable When this bit is set (one) and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator ...
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... The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero. ATmega163(L) 38 1142E–AVR–02/03 ...
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... Timer/Counters The ATmega163 provides three general purpose Timer/Counters – two 8-bit T/Cs and one 16-bit T/C. Timer/Counter2 can optionally be asynchronously clocked from an exter- nal Oscillator. This Oscillator is optimized for use with a 32.768 kHz watch crystal, enabling use of Timer/Counter2 as a Real Time Clock (RTC). Timer/Counter0 and Timer/Counter1 have individual prescaling selection from the same 10-bit prescaler ...
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... The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make the Timer/Counter0 useful for lower speed functions or exact timing functions with infre- quent actions. ATmega163( PCK2 Clear TOSC1 ...
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... Register – TCCR0 • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATmega163 and always read as zero. • Bits 2..0 – CS02, CS01, CS00: Clock Select0, Bit 2, 1, and 0 The Clock Select0 bits 2,1, and 0 define the prescaling source of Timer0. ...
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... Timer/Counter Interrupt Mask Register – TIMSK. When Timer/Counter1 is externally clocked, the external signal is synchronized with the Oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU ATmega163(L) 42 Bit 7 ...
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... The ICP pin logic is shown in Figure 34. Figure 34. ICP Pin Schematic Diagram If the noise canceler function is enabled, the actual trigger condition for the capture event is monitored over four samples, and all four must be equal to activate the Capture Flag. 1142E–AVR–02/03 ATmega163(L) 43 ...
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... COM1B0 bits are written in the same cycle as FOC1B, the new settings will not take effect until next Compare Match or Forced Compare Match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a Compare Match ATmega163(L) 44 Bit ...
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... Input Capture Register – ICR1 – on the rising edge of the Input Capture Pin – ICP. • Bits 5, 4 – Res: Reserved Bits These bits are reserved bits in the ATmega163 and always read as zero. • Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), the Timer/Counter1 is Reset to $0000 in the clock cycle after a Compare A Match ...
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... This temporary register is also used when accessing OCR1A, OCR1B, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program and interrupt routines. ATmega163(L) 46 CS12 CS11 CS10 ...
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... MSB $2A ($4A Read/Write R/W R/W R/W R/W R/W R/W Initial Value Bit $29 ($49) MSB $28 ($48 Read/Write R/W R/W R/W R/W R/W R/W Initial Value ATmega163( LSB R/W R/W R/W R/W R/W R/W R/W R/W R/W R LSB R/W R/W R/W ...
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... Then the Timer/Counter1 and the Output Com- pare Register1A – OCR1A and the Output Compare Register1B – OCR1B, form a dual 8-, 9-, or 10-bit, free-running and glitch-free PWM with outputs on the PD5(OC1A) and PD4(OC1B) pins. ATmega163(L) 48 Bit 15 ...
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... Not connected Not connected Cleared on Compare Match, set on overflow Set on Compare Match, cleared on overflow ATmega163(L) Timer TOP Value 8-bit $00FF (255) 9-bit $01FF (511) 10-bit $03FF(1023) 8-bit $00FF (255) 9-bit $01FF (511) 10-bit $03FF(1023) Timer TOP Value Frequency $00FF (255) ...
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... COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in Table 18. In overflow PWM mode, the output OC1A/OC1B is held low or high only when the Output Compare Register contains TOP. Table 18. PWM Outputs OCR1X = $0000 or TOP Note: ATmega163(L) 50 Synchronized OC1x Latch Unsynchronized OC1x Latch Note Synchronized OC1x Latch ...
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... TIMER INT. MASK TIMER INT. FLAG REGISTER (TIMSK) REGISTER (TIFR T/C CLEAR TIMER/COUNTER2 T/C CLK SOURCE (TCNT2) UP/DOWN 7 0 8-BIT COMPARATOR 7 0 OUTPUT COMPARE REGISTER2 (OCR2) CK SYNCH UNIT PCK2 ATmega163(L) T/C2 CONTROL REGISTER (TCCR2) CK CONTROL PSR2 LOGIC TOSC1 ASYNCH. STATUS REGISTER (ASSR) 51 ...
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... The COM21 and COM20 control bits determine any output pin action following a Com- pare Match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 19. Table 19. Compare Mode Select Note: ATmega163(L) 52 Bit ...
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... CS22 CS21 CS20 Bit $24 ($44) MSB Read/Write R/W R/W R/W Initial Value ATmega163(L) Description Timer/Counter2 is stopped. PCK2 PCK2/8 PCK2/32 PCK2/64 PCK2/128 PCK2/256 PCK2/1024 LSB R/W R/W R/W R/W R TCNT2 53 ...
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... If CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start count- ing from $00 after reaching $FF. The PD7(OC2) pin will be set or cleared according to the settings of COM21/COM20 on a Timer/Counter overflow or when the counter value matches the contents of the Output Compare Register. Refer to Table 21 for details. ATmega163(L) 54 Bit 7 ...
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... Compare Match, up-counting (inverted PWM Not connected Not connected Cleared on compare match, set on overflow Set on compare match, cleared on overflow. Synchronized OC2 Latch Unsynchronized OC2 Latch ATmega163(L) Frequency f /510 TCK0/2 f /510 TCK0/2 f /256 TCK0/2 f /256 TCK0/2 PWM Output OC2 PWM Output OC2 55 ...
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... Timer/Counter mode, i.e executed when TOV2 is set provided that Timer Overflow Interrupt and Global Interrupts are enabled. This also applies to the Timer Out- put Compare Flag and Interrupt. The frequency of the PWM will be Timer Clock Frequency divided by 510. ATmega163(L) 56 Synchronized OC2 Latch Unsynchronized OC2 Latch ...
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... Asynchronous Status Register – ASSR • Bit 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega163 and always read as zero. • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is cleared (zero), Timer/Counter2 is clocked from the internal system clock, CK. When AS2 is set (one), Timer/Counter2 is clocked from the PC6(TOSC1) pin. Pins PC6 and PC7 are connected to a crystal Oscillator and cannot be used as general I/O pins ...
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... ATmega163(L) 58 Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2. 2. Select clock source by setting AS2 as appropriate. ...
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... Safe procedure to ensure that the correct value is read: 1. Write any value to either of the registers OCR2 or TCCR2. 2. Wait for the corresponding Update Busy Flag to be cleared. 3. Read TCNT2. Note that OCR2 and TCCR2 are never modified by hardware, and will always read correctly. ATmega163(L) 59 ...
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... Register – WDTCR • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega163 and will always read as zero. • Bit 4 – WDTOE: Watchdog Turn-off Enable This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will not be disabled ...
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... WDE even though it is set to one before the disable operation starts. Watchdog. Number of WDT WDP2 WDP1 WDP0 Oscillator Cycles 16K cycles 32K cycles 64K cycles 128K cycles 256K cycles 512K cycles 1,024K cycles 2,048K cycles ATmega163(L) Typical Time-out Typical Time-out 0.38 s 0.12 s 0.75 s 0.24 s 1.5 s 0.49 s 3.0 s 0.97 s 6 ...
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... Register – EEARH and EEARL • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega163 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the 512 bytes EEPROM space ...
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... EECR • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega163 and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable When the I bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled ...
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... Keep the AVR RESET active (low) during periods of insufficient power supply 2. Keep the AVR core in Power-down Sleep Mode during periods of low V 3. Store constants in Flash memory if the ability to change memory contents from ATmega163(L) 64 Number of Calibrated Symbol RC Oscillator Cycles ...
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... Serial Peripheral The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega163 and peripheral devices or between several AVR devices. The Interface – SPI ATmega163 SPI includes the following features: • • • • • • • • Figure 41. SPI Block Diagram The interconnection between Master and Slave CPUs with SPI is shown in Figure 42 ...
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... Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possibility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master mode. ATmega163(L) 66 (1) Pin ...
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... When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations. 1142E–AVR–02/03 Bit $0D ($2D) SPIE SPE DORD Read/Write R/W R/W R/W Initial Value ATmega163( MSTR CPOL CPHA SPR1 SPR0 R/W R/W R/W R/W R ...
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... SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alter- natively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set (one), then accessing the SPI Data Register (SPDR). ATmega163( shown in the following table: ck ...
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... WCOL set (one), and then accessing the SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the ATmega163 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is set (one) the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 26) ...
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... UART The ATmega163 features a full duplex (separate Receive and Transmit Registers) Uni- versal Asynchronous Receiver and Transmitter (UART). The main features are: • • • • • • • • • • Data Transmission A block schematic of the UART transmitter is shown in Figure 45. ...
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... The TXEN bit in UCR enables the UART transmitter when set (one). When this bit is cleared (zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART Transmitter will be connected to PD1, which is forced output pin regardless of the setting of the DDD1 bit in DDRD. 1142E–AVR–02/03 ATmega163(L) 71 ...
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... All bits are shifted into the Transmitter Shift Register as they are sampled. Sampling of an incoming character is shown in Figure 47. Note that the description above is not valid when the UART trans- mission speed is doubled. See “Double Speed Transmission” on page 78 for a detailed description. ATmega163(L) 72 1142E–AVR–02/03 ...
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... In 8-bit reception mode (CHR9 in UCSRB cleared), the stop bit is one for an address byte and zero for a data byte. In 9-bit reception mode (CHR9 in UCSRB 1142E–AVR–02/03 (1) 1. This figure is not valid when the UART speed is doubled. See “Double Speed Trans- mission” on page 78 for a detailed description. ATmega163(L) 73 ...
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... Shift Register has been shifted out and no new data has been written to UDR. This Flag is especially useful in half-duplex communications interfaces, where a transmitting appli- cation must enter receive mode and free the communications bus immediately after completing the transmission. ATmega163( set). byte. In the Slave MCUs, the RXC Flag in UCSRA will be set as normal. ...
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... The OR bit is cleared (zero) when data is received and transferred to UDR. • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the ATmega163 and will always read as zero. • Bits 1 – U2X: Double the UART Transmission Speed Setting this bit will reduce the division of the baud rate generator clock from effectively doubling the transfer speed at the expense of robustness. For a detailed description, see “ ...
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... Bit 0 – TXB8: Transmit Data Bit 8 When CHR9 is set (one), TXB8 is the ninth data bit in the character to be transmitted. Baud Rate Generator The Baud Rate generator is a frequency divider which generates baud-rates according to the following equation: • • • ATmega163(L) 76 Bit $0A ($2A) RXCIE ...
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... MHz % Erro ATmega163(L) % Error 2,458 MHz % Error 51 0 0 0 0 3 0 6 0 0 5,0 % Error 4,608 MHz % Error 103 0 119 0,0 ...
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... The UBRRHI contains the four most significant bits, and the UBRR contains the eight least significant bits of the UART Baud Rate. Double Speed The ATmega163 provides a separate UART mode which allows the user to double the communication speed. By setting the U2X bit in the UART Control and Status Register Transmission UCSRA, the UART speed will be doubled ...
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... UBR = 25 UBR = 15 0.0 UBR = 16 UBR = 11 0.0 UBR = 12 UBR = 7 0.0 UBR = 8 UBR = 3 0.0 UBR = 3 UBR = 1 0.0 UBR = 1 UBR = 0 0.0 UBR = 0 ATmega163(L) % Error 2.0000 MHz % Error 0.0 UBR = 103 0.2 0.0 UBR = 51 0.2 0.0 UBR = 25 0.2 0.0 UBR = 16 2.1 0.0 UBR = 12 0.2 ...
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... The operation of the Two-wire Serial Bus is shown as a pulse diagram in Fig- ure 50, including the START and STOP conditions and generation of ACK signal by the bus receiver. Figure 50. Two-wire Serial Bus Timing Diagram The block diagram of the Two-wire Serial Interface is shown in Figure 51. ATmega163(L) 80 Device 1 Device 2 Device 3 ...
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... ADDRESS REGISTER COMPARATOR TWAR INPUT DATA SHIFT SDA REGISTER OUTPUT TWDR START/STOP INPUT SCL AND SYNC OUTPUT ARBITRATION SERIAL CLOCK GENERATOR STATE MACHINE STATUS DECODER ATmega163(L) AND ACK TIMING AND CONTROL CONTROL REGISTER TWCR STATUS STATUS AND REGISTER TWSR 81 ...
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... Two-wire Serial Interface, so all accesses to the Two-wire Serial Interface Address Register – TWAR, Two-wire Serial Interface Sta- tus Register – TWSR, and Two-wire Serial Interface Data Register – TWDR must be complete before clearing this flag. ATmega163(L) 82 Bit 7 ...
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... SDA and SCL are set to high impedance state, and the input signals are ignored. The interface is activated by setting this bit (one). • Bit 1 – Res: Reserved Bit This bit is a reserved bit in the ATmega163 and will always read as zero. 1142E–AVR–02/03 ATmega163(L) ...
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... Serial Bus. • Bits 2..0 – Res: Reserved bits These bits are reserved in ATmega163 and will always read as zero The TWSR is read only. It contains a status code which reflects the status of the Two- wire Serial Interface logic and the Two-wire Serial Bus. There are 26 possible status codes ...
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... TWAR, TWDR, and TWSR must have been com- pleted before clearing this flag. 1142E–AVR–02/03 Bit $02 ($22) TWA6 TWA5 TWA4 Read/Write R/W R/W R/W Initial Value Master Transmitter Master Receiver Slave Receiver Slave Transmitter ATmega163( TWA3 TWA2 TWA1 TWA0 TWGCE R/W R/W R/W R/W R TWAR 0 85 ...
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... Received data can be read from the TWDR Register when the TWINT Flag is set high by hardware. This scheme is repeated until the last byte has been received and a STOP condition is transmitted by writing a logic one to the TWSTO bit in the TWCR Register. ATmega163(L) 86 TWCR TWINT ...
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... Assembly code illustrating operation of the Slave Receiver mode is given at the end of the TWI section. 1142E–AVR–02/03 TWAR TWA6 TWA5 TWA4 Value Device’s Own Slave Address TWCR TWINT TWEA TWSTA Value 0 1 ATmega163(L) TWA3 TWA2 TWA1 TWSTO TWWC TWEN TWA0 TWGCE – TWIE 0 ...
Page 88
... This causes the Two-wire Serial Interface to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in TWCR are affected). The SDA and SCL lines are released and no STOP condition is transmitted. ATmega163(L) 88 1142E–AVR–02/03 ...
Page 89
... No TWDR action TWDR action TWDR action ATmega163(L) Next Action Taken by Two-wire Serial Interface Hard- TWEA ware X SLA+W will be transmitted; ACK or NOT ACK will be received X SLA+W will be transmitted; ACK or NOT ACK will be received X SLA+R will be transmitted; Logic will switch to Master Receiver mode ...
Page 90
... Figure 52. Formats and States in the Master Transmitter Mode Assembly Code Example – Master Transmitter Mode ATmega163( Successfull S SLA W A Transmission to a Slave Receiver $08 $18 Next Transfer Started with a Repeated Start Condition Not Acknowledge A Received After the Slave Address $20 Not Acknowledge Received After a Data ...
Page 91
... TWINT; data has been transmitted, and ACK/NACK has rjmp wait4 ; been received in r16, TWSR ; Check value of TWI Status Register. If status cpi r16, MT_DATA_ACK; different from MT_DATA_ACK ERROR brne ERROR ldi r16, (1<<TWINT) | (1<<TWSTO) | (1<<TWEN) out TWCR, r16 ; Transmit STOP condition ATmega163(L) 91 ...
Page 92
... NOT ACK has been received $50 Data byte has been received; ACK has been returned $58 Data byte has been received; NOT ACK has been returned Figure 53. Formats and States in the Master Receiver Mode ATmega163(L) 92 Application Software Response To TWCR To/from TWDR STA STO TWINT ...
Page 93
... TWCR, r16 ; Clear TWINT bit in TWCR to start reception of ; data. Setting TWEA causes ACK to be returned ; after reception of data byte ;<Receive more data bytes if needed> ;receive next to last data byte. wait8:in r16,TWCR ; Wait for TWINT flag set. This indicates that ATmega163(L) 93 ...
Page 94
... ATmega163(L) 94 sbrs r16, TWINT ; data has been received and ACK returned rjmp wait8 in r16, TWSR ; Check value of TWI Status Register. If status cpi r16, MR_DATA_ACK ; different from MR_DATA_ACK ERROR brne ERROR in r16, TWDR ; Input received data from TWDR. nop ;<do something with received data> ...
Page 95
... Read data byte Read data byte ATmega163(L) Next Action Taken by Two-wire Serial Interface Hardt- TWEA ware 0 Data byte will be received and NOT ACK will be returned 1 Data byte will be received and ACK will be returned 0 Data byte will be received and NOT ACK will be ...
Page 96
... Figure 54. Formats and States in the Slave Receiver Mode Assembly Code Example – Slave Receiver Mode ATmega163(L) 96 Reception of the Own S SLA W Slave Address and One or More Data Bytes. All are Acknowledged Last Data Byte Received is not Acknowledged Arbitration Lost as Master and Addressed as Slave ...
Page 97
... TWCR, r16 ; Clear TWINT bit in TWCR to start reception of ; data. Setting TWEA causes TWI unit to enter ; not addressed slave mode with reckognition of ; own SLA ;<Wait for next data transmission or do something else> ATmega163(L) 97 ...
Page 98
... Data byte in TWDR has been transmitted; NOT ACK has been received $C8 Last data byte in TWDR has been transmitted (TWEA = “0”); ACK has been received Figure 55. Formats and States in the Slave Transmitter Mode ATmega163(L) 98 Application Software Response To TWCR To/from TWDR STA STO TWINT ...
Page 99
... Load data (here, data = 0x55) into TWDR Register out TWDR, r16 ldi r16, (1<<TWINT) | (1<<TWEN) out TWCR, r16 ; Clear TWINT bit in TWCR to start transmission of ; data. Not setting TWEA indicates that NACK should ATmega163(L) ; Enable TWI in Slave 99 ...
Page 100
... No relevant state information available; TWINT = “0” $00 Bus error due to an illegal START or STOP condition TWI Include File ATmega163(L) 100 ; be received after data byte Master signalling end ; of transmission) wait17:in r16,TWCR ; Wait for TWINT flag set. This indicates that sbrs r16, TWINT ...
Page 101
... NACK returned .equ SR_STOP =$A0 ;A STOP condition or repeated START condition ;has been received while still addressed as a ;slave ;***** Miscellanous States ***** .equ NO_INFO =$F8 ;No relevant state information; TWINT = ’0’ .equ BUS_ERROR =$00 ;Bus error due to illegal START or STOP ;condition ATmega163(L) 101 ...
Page 102
... When this bit is set and the BOD is enabled (BODEN Fuse is programmed), a fixed bandgap voltage of nominally 1.22V replaces the positive input to the Analog Compara- tor. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. ATmega163(L) 102 BANDGAP REFERENCE ACBG ...
Page 103
... Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. 1142E–AVR–02/03 ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge 1 1 Comparator Interrupt on Rising Output Edge ATmega163(L) 103 ...
Page 104
... ADCSR is zero), MUX2..0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in Table 38. If ACME is cleared (zero) or ADEN is set (one), PB3 (AIN1) is applied to the negative input to the Analog Comparator. Table 38. Analog Comparator Multiplexed Input ATmega163(L) 104 ACME ADEN MUX2 ...
Page 105
... The ATmega163 features a 10-bit successive approximation ADC. The ADC is con- nected to an 8-channel Analog Multiplexer which allows each pin of Port used as input for the ADC. The ADC contains a Sample and Hold Amplifier which ensures that the input voltage to the ADC is held at a constant level during conversion ...
Page 106
... The ADFR bit in ADCSR selects between the two available modes. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSR. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not ATmega163(L) 106 8-BIT DATA BUS ...
Page 107
... ADC is switched on by setting the ADEN bit in ADCSR. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. 1142E–AVR–02/03 Reset ADEN 7-BIT ADC PRESCALER CK ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE ATmega163(L) 107 ...
Page 108
... Figure 59. ADC Timing Diagram, Extended Conversion (Single Conversion Mode) Cycle Number ADC Clock ADEN ADSC ADIF ADCH ADCL Figure 60. ADC Timing Diagram, Single Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL ATmega163(L) 108 Extended Conversion MUX and REFS Sample & Hold ...
Page 109
... Mode must be selected and the ADC conversion complete interrupt must be enabled. ADEN = 1 ADSC = 0 ADFR = 0 ADIE = 1 sion once the CPU has been halted. rupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. ATmega163(L) Next Conversion Sign and MSB of Result LSB of Result Sample & ...
Page 110
... The value of these bits selects which combination of analog inputs are connected to the ADC. See Table 41 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). Table 41. Input Channel Selections ATmega163(L) 110 Bit 7 ...
Page 111
... When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Com- plete Interrupt is activated. 1142E–AVR–02/03 MUX4..0 01000..11101 11110 11111 Bit $06 ($26) ADEN ADSC ADFR Read/Write R/W R/W R/W Initial Value ATmega163(L) Single-ended Input Reserved 1.22V ( (AGND ADIF ADIE ADPS2 ADPS1 ADPS0 R/W R/W R/W R/W R ...
Page 112
... If ADLAR is cleared (default), the result is right adjusted. • ADC9..0: ADC Conversion result These bits represent the result from the conversion. $000 represents analog ground, and $3FF represents the selected reference voltage minus one LSB. ATmega163(L) 112 ADPS2 ADPS1 ...
Page 113
... The analog part of the ATmega163 and all analog components in the application 2. Keep analog signal paths as short as possible. Make sure analog tracks run over 3. The AVCC pin on the ATmega163 should be connected to the digital V 4. Use the ADC noise canceler function to reduce induced noise from the CPU. ...
Page 114
... Internal Voltage Reference V Bandgap Voltage Reference BG R Reference Input Resistance REF V Input Voltage IN R Analog Input Resistance AIN Notes: 1. Minimum for AVCC is 2.7V. 2. Maximum for AVCC is 5.5V. ATmega163(L) 114 Condition Min Single-ended Conversion REF ADC clock = 200 kHz REF ADC clock = 1 MHz REF ...
Page 115
... DDA7 DDA6 DDA5 Read/Write R/W R/W R/W Initial Value Bit $19 ($39) PINA7 PINA6 PINA5 Read/Write Initial Value N/A N/A N/A ATmega163( present during powerdown without PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 R/W R/W R/W R DDA4 DDA3 DDA2 DDA1 DDA0 R/W ...
Page 116
... Table 44. DDAn Effects on PORTA Pins Note: PORT A Schematics Note that all port pins are synchronized. The synchronization latches are not shown in the figure. Figure 63. PORTA Schematic Diagrams (Pins PA0 - PA7) ATmega163(L) 116 DDAn PORTAn PUD I/O 0 ...
Page 117
... Initial Value Bit $17 ($37) DDB7 DDB6 DDB5 Read/Write R/W R/W R/W Initial Value Bit $16 ($36) PINB7 PINB6 PINB5 Read/Write Initial Value N/A N/A N/A ATmega163( PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 R/W R/W R/W R DDB4 DDB3 DDB2 DDB1 DDB0 R/W R/W R/W R ...
Page 118
... When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB4. When the pin is forced input, the pull-up can still be con- trolled by the PORTB4 bit. See the description of the SPI port for further details. ATmega163(L) 118 DDBn ...
Page 119
... Note that all port pins are synchronized. The synchronization latches are not shown in the figures. Figure 64. PORTB Schematic Diagram (Pins PB0 and PB1) 1142E–AVR–02/ present during Power-down without present during Power-down without caus- CC PUD PUD: PULL-UP DISABLE 2 ATmega163(L) 119 ...
Page 120
... Figure 65. PORTB Schematic Diagram (Pins PB2 and PB3) Figure 66. PORTB Schematic Diagram (Pin PB4) ATmega163(L) 120 MOS PUD PULL- UP PBn RL PWRDN RP WP: WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB PUD: PULL-UP DISABLE MOS PUD PULL- UP PB4 ...
Page 121
... PULL-UP DISABLE MOS PUD PULL- UP PB6 WP: WRITE PORTB WRITE DDRB WD: RL: READ PORTB LATCH RP: READ PORTB PIN READ DDRB RD: SPI ENABLE SPE: MSTR MASTER SELECT PUD: PULL-UP DISABLE ATmega163(L) RD RESET DDB5 C WD RESET PORTB5 MSTR SPE SPI MASTER OUT SPI SLAVE ...
Page 122
... Figure 69. PORTB Schematic Diagram (Pin PB7) ATmega163(L) 122 MOS PUD PULL- UP PB7 WP: WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB SPE: SPI ENABLE MSTR MASTER SELECT PUD: PULL-UP DISABLE RD RESET DDB7 C WD RESET PORTB7 MSTR SPE SPI ClLOCK ...
Page 123
... Initial Value Bit $14 ($34) DDC7 DDC6 DDC5 Read/Write R/W R/W R/W Initial Value Bit $13 ($33) PINC7 PINC6 PINC5 Read/Write Initial Value N/A N/A N/A ATmega163( PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 R/W R/W R/W R DDC4 DDC3 DDC2 DDC1 DDC0 R/W R/W R/W R ...
Page 124
... Two-wire Serial Interface, pin PC1 is disconnected from the port and becomes the Serial Clock I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to capture spikes shorter than the input signal. ATmega163(L) 124 DDCn ...
Page 125
... Port C Schematics Note that all port pins are synchronized. The synchronization latches are not shown in the figure. Figure 70. PORTC Schematic Diagram (Pins PC0 - PC1) 1142E–AVR–02/03 0 PUD 1 PCn 0 1 PUD: PULL-UP DISABLE ATmega163(L) DDCn n SCL/SDA out SCL/SDA in TWEN 125 ...
Page 126
... Figure 71. PORTC Schematic Diagram (Pins PC2 - PC5) Figure 72. PORTC Schematic Diagram (Pins PC6) ATmega163(L) 126 MOS PUD PULL- UP PCn RL RP WP: WRITE PORTC WD: WRITE DDRC RL: READ PORTC LATCH RP: READ PORTC PIN RD: READ DDRC PUD: PULL-UP DISABLE n: 2..5 PUD MOS PULL- UP PC6 0 1 WP: ...
Page 127
... Figure 73. PORTC Schematic Diagram (Pins PC7) 1142E–AVR–02/03 PUD 0 1 PUD: PULL-UP DISABLE ATmega163(L) 127 ...
Page 128
... The Port D Input Pins Address – PIND – is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the PORTD Data Latch is read, and when reading PIND, the logical values present on the pins are read. ATmega163(L) 128 Port Pin Alternate Function ...
Page 129
... Source to the MCU. See the interrupt description for further details, and how to enable the source. 1142E–AVR–02/03 DDDn PORTDn PUD I Input Input Input Output Output 1. n: 7,6…0, pin number. ATmega163(L) (1) Pull Up Comment No Tri-state (Hi-Z) No Tri-state (Hi-Z) Yes PDn will source current if ext. pulled low. No Push-pull Zero Output No Push-pull One Output 129 ...
Page 130
... DDRD0. When the UART forces this pin input, a logical one in PORTD0 will turn on the internal pull-up. Port D Schematics Note that all port pins are synchronized. The synchronization latches are not shown in the figures. Figure 74. PORTD Schematic Diagram (Pin PD0) ATmega163(L) 130 PUD MOS PULL- UP ...
Page 131
... MOS PUD PULL- UP PD1 WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN READ DDRD RD: UART TRANSMIT DATA TXD: TXEN: UART TRANSMIT ENABLE PUD: PULL-UP DISABLE PUD PUD: PULL-UP DISABLE ATmega163(L) RD RESET DDD1 C WD RESET PORTD1 TXEN TXD 131 ...
Page 132
... Figure 77. PORTD Schematic Diagram (Pins PD4 and PD5) Figure 78. PORTD Schematic Diagram (Pin PD6) ATmega163(L) 132 PUD PUD: PULL-UP DISABLE MOS PUD PULL- UP PD6 RL RP WP: WRITE PORTD 0 NOISE CANCELER WD: WRITE DDRD 1 RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD ICNC1 ...
Page 133
... Figure 79. PORTD Schematic Diagram (Pin PD7) 1142E–AVR–02/03 PUD PUD: PULL-UP DISABLE ATmega163(L) 133 ...
Page 134
... Store Program Memory (SPM) instruction can only be executed from the Boot Loader Flash section. The Program Flash memory in ATmega163 is divided into 128 pages of 64 words each. The Boot Loader Flash section is located at the high address space of the Flash, and can be configured through the BOOTSZ Fuses as shown in Table 51. ...
Page 135
... Boot Flash Section 2 (128 x 16) Program Memory Pages BOOTSZ = '01' Application Flash Section 120 (7680 x 16) Boot Flash Section 8 (512 x 16) ATmega163(L) Program Memory Pages BOOTSZ = '10' $0000 Application Flash Section 124 (7936 x 16) $1F7F Boot Flash Section $1F80 4 (256 x 16) ...
Page 136
... LSB in SPMCR and execute SPM within four clock cycles after writ- ing SPMCR. The content of Z6:Z1 is used to address the data in the temporary buffer. Z13:Z7 must point to the page that is supposed to be written. ATmega163(L) 136 BOOTRST Reset Address ...
Page 137
... Boot Loader Lock Bits ATmega163 has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. The user can select: • ...
Page 138
... SPM, or LPM, instruction is executed within four, respectively five, CPU cycles. When BLBSET and SPMEN are cleared, LPM will work as described in “Con- stant Addressing Using The LPM and SPM Instructions” on page 15 and in the Instruction set Manual. ATmega163(L) 138 BLB0 mode BLB02 ...
Page 139
... Z14 Z13 ZL (R30 page select, for page erase and page write word select, for filling temp buffer (must be zero during page write operation) should be zero for all SPM commands, byte select for the LPM instruction. ATmega163( BLB11 BLB02 BLB01 LB2 LB1 4 3 ...
Page 140
... Page Erase and Page Write. In ATmega163, this bit always reads as zero. • Bit 5 – Res: Reserved Bit This bit is a reserved bit in the ATmega163 and always reads as zero. This bit should be written to zero when writing SPMCR. • Bit 4 – ASRE: Application Section Read Enable Before re-entering the Application section, the user software must set this bit together with the SPMEN bit and execute SPM within four clock cycles ...
Page 141
... It is assumed that the interrupts are disabled .equ PAGESIZEB = PAGESIZE*2 not words .org SMALLBOOTSTART Write_page: ; page erase ldi spmcrval, (1<<PGERS) + (1<<SPMEN) call Do_spm ATmega163( This CC ;PAGESIZEB is page size in BYTES, 141 ...
Page 142
... ATmega163(L) 142 ; re-enable the Application Section ldi spmcrval, (1<<ASRE) + (1<<SPMEN) call Do_spm ; transfer data from RAM to Flash page buffer ldi looplo, low(PAGESIZEB) ldi loophi, high(PAGESIZEB) Wrloop r1, Y+ ldi spmcrval, (1<<SPMEN) call Do_spm adiw ZH:ZL, 2 sbiw loophi:looplo, 2 brne Wrloop ...
Page 143
... Program and Data The ATmega163 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 55. The Lock bits can Memory Lock Bits only be erased to “1” with the Chip Erase command. ...
Page 144
... Fuse Bits The ATmega163 has ten Fuse bits, divided in two groups. The Fuse High bits are BOOTSZ1..0 and BOOTRST, and the Fuse Low bits are BODLEVEL, BODEN, SPIEN, and CKSEL3..0. • • • • • • The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed ...
Page 145
... ATmega163. Pulses are assumed least 500ns unless otherwise noted. Signal Names In this section, some pins of the ATmega163 are referenced by signal names describing their functionality during parallel programming, see Figure 81 and Table 56. Pins not described in the following table are referenced by pin names. ...
Page 146
... The Fuse bits are not changed. A Chip Erase must be performed before the Flash is re- programmed. Load Command “Chip Erase” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. ATmega163(L) 146 Signal Name in Programming Mode Pin Name ...
Page 147
... Set XA1, XA0 to “01”. This enables data loading. 3. Set DATA = Data High Byte ($00 - $FF). 4. Give XTAL1 a positive pulse. This loads the data byte. 1. Set BS1 to “1”. This selects High Data Byte. 2. Give PAGEL a positive pulse. This latches the data High Byte. ATmega163(L) 147 ...
Page 148
... K. Repeat A through J 128 times or until all data has been programmed. Figure 82. Programming the Flash Waveforms DY/BSY RESET PAGEL ATmega163(L) 148 1. 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “1”. This selects high address. 3. Set DATA = Address High Byte ($00 - $1F). ...
Page 149
... The command needs only be loaded once when writing or reading multiple memory locations. Address high byte needs only be loaded before programming a new 256 word page in the EEPROM. Skip writing the data value $FF, that is the contents of the entire EEPROM after a Chip Erase. ATmega163(L) 149 ...
Page 150
... Flash” on page 147 for details on Command and Data loading Load Command “0100 0000” Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high. ATmega163(L) 150 DATA $11 ADDR ...
Page 151
... DATA (“0” means programmed). Bit 2..1 = BOOTSZ1..0 Fuse bits Bit 0 = BOOTRST Fuse bit read at DATA (“0” means programmed). Bit 5 = Boot Lock bit12 Bit 4 = Boot Lock bit11 Bit 3 = Boot Lock bit02 Bit 2 = Boot Lock bit01 Bit 1 = Lock bit2 Bit 0 = Lock bit1 ATmega163(L) 151 ...
Page 152
... Flash for details on Command and Address loading Load Command “0000 1000” Load Address Low Byte, $00. 3. Set OE to “1”. ATmega163(L) 152 DATA. Set OE to “0”, and BS1 to “1”. The Calibaration byte can now be read at DATA. 1142E–AVR–02/03 ...
Page 153
... OE High to DATA Tri-stated OHDZ valid for the Write EEPROM, Write Fuse Bits and Write Lock Bits WLRH commands valid for the Chip Erase command. WLRH_CE valid for the Write Flash command. WLRH_FLASH ATmega163(L) XLWL XLDX t PLBX BVWL t WLWH PLWL WLRL t OLDV = 25 C ± 10%, V ...
Page 154
... The device can be clocked by any clock option during Serial Programming. The mini- mum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 MCU clock cycles High: > 2 MCU clock cycles ATmega163(L) 154 (1) ATmega163 MOSI PB5 MISO PB6 SCK PB7 ...
Page 155
... Serial Programming When writing serial data to the ATmega163, data is clocked on the rising edge of SCK. Algorithm When reading data from the ATmega163, data is clocked on the falling edge of SCK. See Figure 87, Figure 88 and Table 62 for timing details. To program and verify the ATmega163 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 61): 1 ...
Page 156
... Programming or erasing non-volatile memory from software, using SPM or the EEPROM interface. See Table 60 for a sum- mary of programming times. Table 60. Maximum Programming Times for Non-volatile Memory Notes: ATmega163(L) 156 before programming the next page chip-erased device contains $FF in WD_FLASH value. ...
Page 157
... Figure 87. Serial Programming Waveforms 1142E–AVR–02/03 SERIAL DATA INPUT MSB PB5 (MOSI) SERIAL DATA OUTPUT MSB PB6 (MISO) SERIAL CLOCK INPUT PB7(SCK) SAMPLE ATmega163(L) LSB LSB 157 ...
Page 158
... Low byte High Byte data out data in don’t care 1 = lock bit lock bit Boot Lock Bit01 Boot Lock Bit02 Boot Lock Bit11 Boot Lock Bit12 CKSEL0 Fuse CKSEL1 Fuse CKSEL2 Fuse CKSEL3 Fuse, B= BODEN Fuse, C= BODLEVEL Fuse, D= BOOTRST Fuse, E= BOOTSZ0 Fuse, F= BOOTSZ1 Fuse ATmega163(L) 158 Instruction Format Byte 2 ...
Page 159
... Oscillator Period (V = 4.0 - 5.5 V) CLCL CC t SCK Pulse Width High SHSL t SCK Pulse Width Low SLSH t MOSI Setup to SCK High OVSH t MOSI Hold after SCK High SHOX t SCK Low to MISO Valid SLIV ATmega163( SLSH SHOX t SHSL t SLIV = - Min Typ Max 0 250 0 125 ...
Page 160
... A,B,C,D) Input Leakage I IL Current I/O pin Input Leakage I IH Current I/O pin RRST Reset Pull-up Resistor R I/O Pin Pull-up Resistor I/O ATmega163(L) 160 *NOTICE: +0.5V CC Condition Min (Except XTAL1) -0.5 (XTAL1), CKSEL3 fuse -0.5 programmed (XTAL1), CKSEL3 fuse -0.5 ...
Page 161
... WDT disabled - 2. 4.0V CC may exceed the related specification. Pins are not guaranteed to sink current greater OL may exceed the related specification. Pins are not guaranteed to source current OH ATmega163(L) Typ Max Units 5.0 mA 15 15.0 µA <1 4.0 µ 750 ns 500 161 ...
Page 162
... External Clock Drive Table 63. External Clock Drive Table 64. External RC Oscillator, typical frequencies Note: ATmega163(L) 162 Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL 100 31.5 6.5 R should be in the range 3k - 100k , and C should be at least 20pF. The C values given in the table includes pin capacitance ...
Page 163
... Two-wire Serial Interface Characteristics Table 65 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega163 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 90. Table 65. Two-wire Serial Bus Requirements Symbol Parameter V Input Low-voltage ...
Page 164
... Figure 90. Two-wire Serial Bus Timing SCL t t SU;STA HD;STA SDA ATmega163(L) 164 t HIGH LOW LOW t HD;DAT t t SU;DAT 1142E–AVR–02/03 SU;STO t BUF ...
Page 165
... Timer enabled and Power-down mode with Watchdog Timer disabled represents the dif- ferential current drawn by the Watchdog Timer. Figure 91. Analog Comparator Offset Voltage vs, Common Mode Voltage (V 1142E–AVR–02/03 • f, where C = load capacitance 0.5 1 1.5 Common Mode Voltage (V) ATmega163(L) = operating voltage and f = average switching ˚ 2.5 3 3.5 4 4.5 • 5V ˚ 5 165 ...
Page 166
... Figure 92. Analog Comparator Offset Voltage vs. Common Mode Voltage (V Figure 93. Analog Comparator Input Leakage Current (V ATmega163(L) 166 0.5 1 Common Mode Voltage ( -10 0 0.5 1 1 ˚ ˚ A 1 3.5 4 4.5 5 5 (V) IN 1142E–AVR–02/03 = 2.7V) CC ...
Page 167
... Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 95. Pull-up Resistor Current vs. Input Voltage (V 1142E–AVR–02/03 1600 1400 1200 1000 800 600 400 200 0 2 2.5 3 3.5 120 ˚ A 100 ˚ 0.5 1 1.5 2 ATmega163( ˚ ˚ 4 5V) CC 2.5 3 3 (V) OP 167 ...
Page 168
... Figure 96. Pull-up Resistor Current vs. Input Voltage (V Figure 97. I/O Pin Sink Current vs. Output Voltage (V ATmega163(L) 168 ˚ ˚ 0 0 2.7V) CC 1.5 2 2.5 3 ( ˚ ˚ A 1.5 2 2.5 3 (V) OL 1142E–AVR–02/03 ...
Page 169
... Figure 98. I/O Pin Source Current vs. Output Voltage (V Figure 99. I/O Pin Sink Current vs. Output Voltage (V 1142E–AVR–02/ ˚ ˚ 0 0.5 V ATmega163(L) = 5V) CC 2.5 3 3.5 4 4 2.7V ˚ ˚ 1.5 2 (V) OL 169 ...
Page 170
... Figure 100. I/O Pin Source Current vs. Output Voltage (V Figure 101. I/O Pin Input Threshold vs. V ATmega163(L) 170 ˚ ˚ 0.5 1 2.5 2 1.5 1 0.5 0 2.7 = 2.7V) CC 1 4.0 5 1142E–AVR–02/03 ...
Page 171
... Figure 102. I/O Pin Input Hysteresis vs. V 1142E–AVR–02/03 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4.0 ATmega163( 5 171 ...
Page 172
... ADEN $05 ($25) ADCH ADC Data Register High Byte $04 ($24) ADCL ADC Data Register Low Byte $03 ($23) TWDR Two-wire Serial Interface Data Register $02 ($22) TWAR TWA6 $01 ($21) TWSR TWS7 ATmega163(L) 172 Bit 6 Bit 5 Bit 4 Bit – – – – SP6 SP5 SP4 ...
Page 173
... Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. 1142E–AVR–02/03 Bit 6 Bit 5 Bit 4 Bit 3 ATmega163(L) Bit 2 Bit 1 Bit 0 Page 82 173 ...
Page 174
... Branch if Half Carry Flag Set BRHC k Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared ATmega163(L) 174 Operation Flags Z,C,N,V Z,C,N,V,H Rdh:Rdl Rdh:Rdl + K Z,C,N,V Z,C,N,V,H ...
Page 175
... Clear Signed Test Flag SEV Set Twos Complement Overflow. CLV Clear Twos Complement Overflow SET Set T in SREG CLT Clear T in SREG SEH Set Half Carry Flag in SREG 1142E–AVR–02/03 ATmega163( then None then None Rd Rr None Rd+1:Rd Rr+1:Rr None ...
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... Instruction Set Summary (Continued) CLH Clear Half Carry Flag in SREG NOP No Operation SLEEP Sleep WDR Watchdog Reset ATmega163(L) 176 None (see specific descr. for Sleep function) None (see specific descr. for WDR/timer) None 1142E–AVR–02/03 ...
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... Wide, Plastic Dual Inline Package (PDIP) 1142E–AVR–02/03 Ordering Code Package ATmega163L-4AC 44A ATmega163L-4PC 40P6 ATmega163L-4AI 44A ATmega163L-4PI 40P6 ATmega163-8AC 44A ATmega163-8PC 40P6 ATmega163-8AI 44A ATmega163-8PI 40P6 Package Type ATmega163(L) Operation Range Commercial ( Industrial (- Commercial ( Industrial (- 177 ...
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... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATmega163(L) 178 B PIN 1 IDENTIFIER ...
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... San Jose, CA 95131 R 1142E–AVR–02/03 D PIN 0º ~ 15º REF SYMBOL eB TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) ATmega163(L) COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE A – – 4.826 A1 0.381 – – D 52.070 – 52.578 Note ...
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... Erratas ATmega163(L) Errata • • Rev. F • • • • 6. Increased Interrupt Latency 5. Interrupts Abort TWI Power-down 4. TWI Master Does not Accept Spikes on Bus Lines 3. TWCR Write Operation Ignored ATmega163(L) 180 Increased Interrupt Latency Interrupts Abort TWI Power-down TWI Master Does not Accept Spikes on Bus Lines ...
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... Make sure this issue is not harmful to the application. When the two-wire Serial Interface operates in Slave mode, frames may be unde- tected if the CPU frequency is less than 64 times the bus frequency. Problem Fix/Workaround Ensure that the CPU frequency is at least 64 times the TWI bus frequency. ATmega163(L) 181 ...
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... Change Log This section containes a log on the changes made to the data sheet for ATmega163. All refereces to pages in Change Log, are referred to this document. Changes from Rev. 1. Added “Not Recommend for New Designs. Use ATmega16.”. 1142C-09/01 to Rev. 1142D-09/02 Changes from Rev. ...
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... Memory Access Times and Instruction Execution Timing .................................. 16 I/O Memory ......................................................................................................... 17 Reset and Interrupt Handling .............................................................................. 21 Sleep Modes....................................................................................................... 35 Calibrated Internal RC Oscillator ........................................................................ 37 Timer/Counter Prescalers ................................................................................... 39 8-bit Timer/Counter0........................................................................................... 40 16-bit Timer/Counter1......................................................................................... 42 8-bit Timer/Counter 2 .......................................................................................... 51 Preventing EEPROM Corruption ........................................................................ 64 SS Pin Functionality............................................................................................ 66 Data Modes ........................................................................................................ 67 Data Transmission.............................................................................................. 70 Data Reception ................................................................................................... 72 UART Control ..................................................................................................... 74 Double Speed Transmission............................................................................... 78 ATmega163(L) i ...
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... The Analog Comparator................................................................... 102 Analog to Digital Converter ............................................................. 105 I/O Ports............................................................................................. 115 Memory Programming...................................................................... 134 Electrical Characteristics................................................................. 160 External Clock Drive Waveforms .................................................... 161 External Clock Drive......................................................................... 162 ATmega163(L) ii Two-wire Serial Interface Modes ........................................................................ 85 Master Transmitter Mode.................................................................................... 86 Master Receiver Mode........................................................................................ 86 Slave Receiver Mode.......................................................................................... 87 Slave Transmitter Mode...................................................................................... 88 Miscellaneous States ...
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... Instruction Set Summary ................................................................. 174 Ordering Information........................................................................ 177 Packaging Information ..................................................................... 178 Erratas ............................................................................................... 180 Change Log ....................................................................................... 182 Table of Contents .................................................................................. i 1142E–AVR–02/03 44A ................................................................................................................... 178 40P6 ................................................................................................................. 179 ATmega163(L) Errata Rev. F ........................................................................... 180 Changes from Rev. 1142C-09/01 to Rev. 1142D-09/02................................... 182 Changes from Rev. 1142D-09/09 to Rev. 1142E-02/03 ................................... 182 ATmega163(L) iii ...
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... ATmega163(L) iv 1142E–AVR–02/03 ...
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... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...