ATMEGA163-8PC Atmel, ATMEGA163-8PC Datasheet - Page 10
ATMEGA163-8PC
Manufacturer Part Number
ATMEGA163-8PC
Description
IC AVR MCU 16K A/D 8MHZ 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA163-8AC.pdf
(187 pages)
Specifications of ATMEGA163-8PC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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The General Purpose
Register File
The X-register, Y-register, and
Z-register
10
ATmega163(L)
Figure 7 shows the structure of the 32 general purpose working registers in the CPU.
Figure 7. AVR CPU General Purpose Working Registers
All the register operating instructions in the instruction set have direct and single cycle
access to all registers. The only exception is the five constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register, and
the LDI instruction for load immediate constant data. These instructions apply to the
second half of the registers in the Register File – R16..R31. The general SBC, SUB, CP,
AND, and OR and all other operations between two registers or on a single register
apply to the entire Register File.
As shown in Figure 7, each register is also assigned a data memory address, mapping
them directly into the first 32 locations of the user Data Space. Although not being phys-
ically implemented as SRAM locations, this memory organization provides great
flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any
register in the file.
The registers R26..R31 have some added functions to their general purpose usage.
These registers are address pointers for indirect addressing of the Data Space. The
three indirect address registers X, Y, and Z are defined as:
Figure 8. The X-, Y-, and Z-registers
X - register
Y - register
Z - register
Registers
Purpose
Working
General
15
7
R27 ($1B)
15
7
R29 ($1D)
15
7
R31 ($1F)
7
XH
YH
ZH
R13
R14
R15
R16
R17
R26
R27
R28
R29
R30
R31
R0
R1
R2
…
…
0
0
0
0
XL
7
R26 ($1A)
YL
7
R28 ($1C)
ZL
7
R30 ($1E)
Addr.
$0D
$1C
$1D
$0E
$0F
$1A
$1B
$1E
$1F
$00
$01
$02
$10
$11
X-register High Byte
Y-register High Byte
Z-register High Byte
X-register Low Byte
Y-register Low Byte
Z-register Low Byte
0
0
0
1142E–AVR–02/03
0
0
0
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