ATMEGA163-8PC Atmel, ATMEGA163-8PC Datasheet - Page 68
ATMEGA163-8PC
Manufacturer Part Number
ATMEGA163-8PC
Description
IC AVR MCU 16K A/D 8MHZ 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA163-8AC.pdf
(187 pages)
Specifications of ATMEGA163-8PC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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The SPI Status Register –
SPSR
68
ATmega163(L)
• Bit 5 – DORD: Data Order
When the DORD bit is set (one), the LSB of the data word is transmitted first.
When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared
(zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be
cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-
enable SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is
low when idle. Refer to Figure 43 and Figure 44 for additional information.
• Bit 2 – CPHA: Clock Phase
Refer to Figure 43 and Figure 44 for the functionality of this bit.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator
Clock frequency f
Table 26. Relationship Between SCK and the Oscillator Frequency
• Bit 7 – SPIF : SPI Interrupt Flag
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is gener-
ated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and
is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is
cleared by hardware when executing the corresponding Interrupt Handling Vector. Alter-
natively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set
(one), then accessing the SPI Data Register (SPDR).
Bit
$0E ($2E)
Read/Write
Initial Value
SPI2X
0
0
0
0
1
1
1
1
SPIF
R
7
0
ck
is shown in the following table:
WCOL
SPR1
R
6
0
0
0
1
1
0
0
1
1
5
–
R
0
SPR0
R
4
–
0
0
1
0
1
0
1
0
1
R
3
–
0
SCK Frequency
f
f
f
f
f
f
f
f
ck
ck
ck
ck
ck
ck
ck
ck
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
R
2
–
0
R
1
–
0
SPI2X
R/W
0
0
1142E–AVR–02/03
SPSR
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