ATTINY12-8SI Atmel, ATTINY12-8SI Datasheet - Page 34

• Manufacturer Part Number: ATTINY12-8SI
• Description: IC AVR MCU 1K 5V 8MHZ IND SO-8
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY12-8SI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: POR, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1 x 8 bit
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Ram Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: No
• Other names: ATTINY128SI

General Interrupt Flag
Register – GIFR
Timer/Counter Interrupt Mask
Register – TIMSK
34
ATtiny11/12
• Bit 7 - Res: Reserved Bit
This bit is a reserved bit in the ATtiny11/12 and always reads as zero.
• Bit 6 - INTF0: External Interrupt Flag0
When an edge on the INT0 pin triggers an interrupt request, the corresponding interrupt
flag, INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt
enable bit, INT0 bit in GIMSK, are set (one), the MCU will jump to the interrupt vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be
cleared by writing a logical one to it. The flag is always cleared when INT0 is configured
as level interrupt.
• Bit 5 - PCIF: Pin Change Interrupt Flag
When an event on any input or I/O pin triggers an interrupt request, PCIF becomes set
(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to
the interrupt vector at address $002. The flag is cleared when the interrupt routine is
executed. Alternatively, the flag can be cleared by writing a logical one to it.
• Bits 4..0 - Res: Reserved Bits
These bits are reserved bits in the ATtiny11/12 and always read as zero.
• Bit 7..2 - Res: Reserved Bits
These bits are reserved bits in the ATtiny11/12 and always read as zero.
• Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector
$003) is executed if an overflow in Timer/Counter0 occurs, i.e., when the Overflow Flag
(Timer0) is set (one) in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 0 - Res: Reserved Bit
This bit is a reserved bit in the ATtiny11/12 and always reads as zero.
Bit
$3A
Read/Write
Initial Value
Bit
$39
Read/Write
Initial Value
R
7
0
-
R
7
0
-
INTF0
R/W
0
6
R
6
0
-
PCIF
R/W
5
0
R
5
0
-
R
4
0
-
R
4
0
-
R
3
0
-
R
3
0
-
R
2
0
-
R
2
0
-
TOIE0
R/W
R
1
0
1
0
-
1006F–AVR–06/07
R
R
0
0
0
0
-
-
TIMSK
GIFR