ATTINY12-8SI Atmel, ATTINY12-8SI Datasheet - Page 37

• Manufacturer Part Number: ATTINY12-8SI
• Description: IC AVR MCU 1K 5V 8MHZ IND SO-8
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY12-8SI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: POR, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1 x 8 bit
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Ram Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: No
• Other names: ATTINY128SI

Register Description
Port B Data Register – PORTB
Port B Data Direction Register
– DDRB
Port B Input Pins Address –
PINB
Port B as General Digital I/O
1006F–AVR–06/07
Note:
The Port B Input Pins address – PINB – is not a register, and this address enables
access to the physical value on each Port B pin. When reading PORTB, the Port B Data
Latch is read, and when reading PINB, the logical values present on the pins are read.
The lowermost five pins in port B have equal functionality when used as digital I/O pins.
PBn, General I/O pin: The DDBn bit in the DDRB register selects the direction of this
pin, if DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero),
PBn is configured as an input pin. If PORTBn is set (one) when the pin is configured as
an input pin, the MOS pull-up resistor is activated. On ATtiny12 this feature can be dis-
abled by setting the Pull-up Disable (PUD) bit in the MCUCR register. To switch the pull-
up resistor off, the PORTBn can be cleared (zero), the pin can be configured as an out-
put pin, or in ATtiny12, the PUD bit can be set. The port pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Table 17. DDBn Effects on Port B Pins
n: 4,3…0, pin number.
Note that in ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output.
Because this pin is used for 12V programming, there is no ESD protection diode limiting
the voltage on the pin to V
the voltage on this pin does not rise above V
cause the MCU to reset or enter programming mode unintentionally.
Bit
$18
Read/Write
Initial Value
Bit
$17
Read/Write
Initial Value
Bit
$16
Read/Write
Initial Value
DDBn
0
0
1
1
DDB5 is only available in ATtiny12.
PORTBn
0
1
0
1
R
R
R
7
0
7
0
7
0
-
-
-
Output
Output
Input
Input
I/O
R
R
R
6
0
6
0
6
0
-
-
-
CC
+ 0.5V. Thus, special care should be taken to ensure that
(DDB5)
Pull-up
PINB5
R(/W)
N/A
Yes
R
5
R
0
5
0
5
No
No
No
-
PORTB4
PINB4
DDB4
R/W
R/W
Comment
Tri-state (Hi-Z)
PBn will source current if ext. pulled low. In ATtiny12
pull-ups can be disabled by setting the PUD bit.
Push-pull Zero Output
Push-pull One Output
N/A
R
4
0
4
0
4
CC
PORTB3
PINB3
DDB3
R/W
R/W
+ 1V during normal operation. This may
N/A
3
0
3
0
3
R
PORTB2
PINB2
DDB2
R/W
R/W
N/A
R
2
0
2
0
2
PORTB1
PINB1
DDB1
ATtiny11/12
R/W
R/W
N/A
R
1
0
1
0
1
PORTB0
PINB0
DDB0
R/W
R/W
N/A
R
0
0
0
0
0
PORTB
DDRB
PINB
37