ATMEGA128L-8AI Atmel, ATMEGA128L-8AI Datasheet - Page 139
![IC AVR MCU 128K 8MHZ LV 64-TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA128L-8AI
Manufacturer Part Number
ATMEGA128L-8AI
Description
IC AVR MCU 128K 8MHZ LV 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128L-8AI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA128L8AI
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA128L-8AI
Manufacturer:
AT
Quantity:
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Part Number:
ATMEGA128L-8AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
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Extended
Timer/Counter
Interrupt Mask
Register – ETIMSK
2467V–AVR–02/11
• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding interrupt
vector
• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match Interrupt is enabled. The corresponding
interrupt vector (See
is set.
• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match Interrupt is enabled. The corresponding
interrupt vector (See
is set.
• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 overflow interrupt is enabled. The corresponding interrupt vector
(See
Note:
• Bit 7:6 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be set to zero when ETIMSK is written.
• Bit 5 – TICIE3: Timer/Counter3, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Input Capture Interrupt is enabled. The corresponding interrupt
vector (See
• Bit 4 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare A Match Interrupt is enabled. The corresponding
interrupt vector (See
ETIFR, is set.
• Bit 3 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare B Match Interrupt is enabled. The corresponding
interrupt vector (See
ETIFR, is set.
Bit
Read/Write
Initial Value
“Interrupts” on page
(See “Interrupts” on page
This register is not available in ATmega103 compatibility mode.
“Interrupts” on page
R
7
–
0
“Interrupts” on page
“Interrupts” on page
“Interrupts” on page
“Interrupts” on page
R
6
–
0
59) is executed when the TOV1 flag, located in TIFR, is set.
TICIE3
R/W
5
0
59.) is executed when the ICF1 flag, located in TIFR, is set.
59) is executed when the ICF3 flag, located in ETIFR, is set.
OCIE3A
R/W
4
0
59) is executed when the OCF1A flag, located in TIFR,
59) is executed when the OCF1B flag, located in TIFR,
59) is executed when the OCF3A flag, located in
59) is executed when the OCF3B flag, located in
OCIE3B
R/W
3
0
TOIE3
R/W
2
0
OCIE3C
R/W
1
0
OCIE1C
R/W
ATmega128
0
0
ETIMSK
139
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