ATMEGA323-8PC Atmel, ATMEGA323-8PC Datasheet - Page 52

• Manufacturer Part Number: ATMEGA323-8PC
• Description: IC AVR MCU 32K 8MHZ COM 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323-8PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA3238PC

Asynchronous Status
Register – ASSR
52
ATmega323(L)
Table 16. PWM Outputs OCRn = $00 or $FF
Note:
In up/down PWM mode, the Timer Overflow Flag, TOV0 or TOV2, is set when the
counter advances from $00. In overflow PWM mode, the Timer Overflow Flag is set as
in normal Timer/Counter mode. Timer Overflow Interrupt0 and 2 operate exactly as in
normal Timer/Counter mode, i.e., they are executed when TOV0 or TOV2 are set pro-
vided that Timer Overflow Interrupt and Global Interrupts are enabled. This does also
apply to the Timer Output Compare Flag and interrupt.
• Bit 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATmega323 and always read as zero.
• Bit 3 – AS2: Asynchronous Timer/Counter2
When AS2 is cleared (zero), Timer/Counter2 is clocked from the internal system clock,
CK. When AS2 is set (one), Timer/Counter2 is clocked from the TOSC1 pin. Pins PC6
and PC7 are connected to a crystal Oscillator and cannot be used as general I/O pins.
When the value of this bit is changed, the contents of TCNT2, OCR2, and TCCR2 might
be corrupted.
• Bit 2 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes
set (one). When TCNT2 has been updated from the temporary storage register, this bit
is cleared (zero) by hardware. A logical zero in this bit indicates that TCNT2 is ready to
be updated with a new value.
• Bit 1 – OCR2UB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes
set (one). When OCR2 has been updated from the temporary storage register, this bit is
cleared (zero) by hardware. A logical zero in this bit indicates that OCR2 is ready to be
updated with a new value.
• Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes
set (one). When TCCR2 has been updated from the temporary storage register, this bit
is cleared (zero) by hardware. A logical zero in this bit indicates that TCCR2 is ready to
be updated with a new value.
Bit
$22 ($22)
Read/Write
Initial Value
COMn1
1. n = 0 or 2
1
1
1
1
In overflow PWM mode, the table above is only valid for OCRn = $FF.
R
7
–
0
R
6
–
0
COMn0
0
0
1
1
R
5
–
0
R
4
–
0
(1)
AS2
R/W
OCRn
3
0
$FF
$FF
$00
$00
TCN2UB
R
2
0
OCR2UB
R
1
0
Output PWMn
TCR2UB
H
H
L
L
1457G–AVR–09/03
R
0
0
ASSR