ATMEGA323-8PC Atmel, ATMEGA323-8PC Datasheet - Page 66
![IC AVR MCU 32K 8MHZ COM 40DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA323-8PC
Manufacturer Part Number
ATMEGA323-8PC
Description
IC AVR MCU 32K 8MHZ COM 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA323L-4PC.pdf
(247 pages)
Specifications of ATMEGA323-8PC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA3238PC
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EEPROM Read/Write
Access
The EEPROM Address
Register – EEARH and EEARL
The EEPROM Data Register –
EEDR
66
ATmega323(L)
The EEPROM Access Registers are accessible in the I/O space.
The write access time is in the range of 1.9 - 3.8 ms, depending on the frequency of the
calibrated RC Oscillator. See Table 25 for details. A self-timing function, however, lets
the user software detect when the next byte can be written. If the user code contains
code that writes the EEPROM, some precautions must be taken. In heavily filtered
power supplies, V
device for some period of time to run at a voltage lower than specified as minimum for
the clock frequency used. CPU operation under these conditions is likely to cause the
Program Counter to perform unintentional jumps and possibly execute the EEPROM
write code. To secure EEPROM integrity, the user is advised to use an external under-
voltage reset circuit or the internal Brown-out Detector in this case.
In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-
lowed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
• Bits 15..10 – Res: Reserved Bits
These bits are reserved bits in the ATmega323 and will always read as zero.
• Bits 9..0 – EEAR9..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address
in the 1K bytes EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 1,023. The initial value of EEAR is undefined. A proper value must be
written before the EEPROM may be accessed.
• Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to
the EEPROM in the address given by the EEAR Register. For the EEPROM read oper-
ation, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
Bit
$1F ($3F)
$1E ($3E)
Read/Write
Initial Value
Bit
$1D ($3D)
Read/Write
Initial Value
EEAR7
MSB
R/W
R/W
15
R
X
–
7
0
7
0
CC
is likely to rise or fall slowly on Power-up/down. This causes the
EEAR6
R/W
R/W
14
R
X
–
6
0
6
0
EEAR5
R/W
R/W
13
R
X
–
5
0
5
0
EEAR4
R/W
R/W
12
R
X
–
4
0
4
0
EEAR3
R/W
R/W
11
R
X
–
3
0
3
0
EEAR2
R/W
R/W
10
R
X
–
2
0
2
0
EEAR9
EEAR1
R/W
R/W
R/W
X
X
9
1
1
0
EEAR8
EEAR0
R/W
LSB
R/W
R/W
1457G–AVR–09/03
X
X
8
0
0
0
EEARH
EEARL
EEDR
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