ATMEGA161L-4PC Atmel, ATMEGA161L-4PC Datasheet - Page 11
ATMEGA161L-4PC
Manufacturer Part Number
ATMEGA161L-4PC
Description
IC AVR MCU 16K LV 4MHZ COM 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA161-8AC.pdf
(159 pages)
Specifications of ATMEGA161L-4PC
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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ALU – Arithmetic Logic
Unit
Self-programmable Flash
Program Memory
EEPROM Data Memory
1228D–AVR–02/07
In the different Addressing modes, these address registers have functions as fixed dis-
placement, automatic increment and decrement (see the descriptions for the different
instructions).
The high-performance AVR ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, ALU operations between regis-
ters in the Register File are executed. The ALU operations are divided into three main
categories – arithmetic, logical and bit functions. ATmega161 also provides a powerful
multiplier supporting both signed/unsigned multiplication and fractional format. See the
Instruction Set section for a detailed description.
The ATmega161 contains 16K bytes of On-chip Self-programmable and In-System Pro-
grammable Flash memory for program storage. Since all instructions are 16- or 32-bit
words, the Flash is organized as 8K x 16. The Flash memory has an endurance of at
least 1,000 write/erase cycles. The ATmega161 Program Counter (PC) is 13 bits wide,
thus addressing the 8,192 Program memory locations.
See page 110 for a detailed description of Flash data downloading.
See page 13 for the different Program Memory Addressing modes.
The ATmega161 contains 512 bytes of data EEPROM memory. It is organized as a sep-
arate data space in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles per location. The interface between the
EEPROM and the CPU is described on page 60, specifying the EEPROM Address Reg-
isters, the EEPROM Data Register and the EEPROM Control Register.
For the SPI data downloading, see page 125 for a detailed description.
ATmega161(L)
11
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