ATMEGA161L-4PC Atmel, ATMEGA161L-4PC Datasheet - Page 53
ATMEGA161L-4PC
Manufacturer Part Number
ATMEGA161L-4PC
Description
IC AVR MCU 16K LV 4MHZ COM 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA161-8AC.pdf
(159 pages)
Specifications of ATMEGA161L-4PC
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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Timer/Counter1 Register –
TCNT1H AND TCNT1L
1228D–AVR–02/07
• Bits 2, 1, 0
The Clock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1.
Table 16. Clock 1 Prescale Select
The Stop condition provides a Timer Enable/Disable function. The CK down divided
modes are scaled directly from the CK Oscillator clock. If the external pin modes are
used for Timer/Counter1, transitions on PB1/(T1) will clock the counter even if the pin is
configured as an output. This feature can give the user software control of the counting.
This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To
ensure that both the high and low bytes are read and written simultaneously when the
CPU accesses these registers, the access is performed using an 8-bit temporary regis-
ter (TEMP). This temporary register is also used when accessing OCR1A, OCR1B, and
ICR1. If the main program and interrupt routines perform access to registers using
TEMP, interrupts must be disabled during access from the main program and interrupt
routines.
•
When the CPU writes to the High byte TCNT1H, the written data is placed in the TEMP
Register. Next, when the CPU writes the Low byte TCNT1L, this byte of data is com-
bined with the byte data in the TEMP Register and all 16 bits are written to the TCNT1
Timer/Counter1 Register simultaneously. Consequently, the High byte TCNT1H must
be accessed first for a full 16-bit register write operation.
•
When the CPU reads the Low byte TCNT1L, the data of the Low byte TCNT1L is sent to
the CPU and the data of the High byte TCNT1H is placed in the TEMP Register. When
the CPU reads the data in the High byte TCNT1H, the CPU receives the data in the
TEMP Register. Consequently, the Low byte TCNT1L must be accessed first for a full
16-bit register read operation.
Bit
$2D ($4D)
$2C ($4C)
Read/Write
Initial Value
CS12
TCNT1 Timer/Counter1 Write
TCNT1 Timer/Counter1 Read
0
0
0
0
1
1
1
1
MSB
R/W
R/W
–
15
CS11
7
0
0
CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0
0
0
1
1
0
0
1
1
R/W
R/W
14
6
0
0
CS10
0
1
0
1
0
1
0
1
R/W
R/W
13
5
0
0
Description
Stop, the Timer/Counter1 is stopped.
CK
CK/8
CK/64
CK/256
CK/1024
External Pin T1, falling edge
External Pin T1, rising edge
R/W
R/W
12
4
0
0
R/W
R/W
11
3
0
0
R/W
R/W
10
2
0
0
ATmega161(L)
R/W
R/W
9
1
0
0
LSB
R/W
R/W
8
0
0
0
TCNT1H
TCNT1L
53
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