PIC16C925/CL Microchip Technology, PIC16C925/CL Datasheet - Page 68

• Manufacturer Part Number: PIC16C925/CL
• Description: IC MCU EPROM 4KX14 LCDDVR 68CLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C925/CL

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: EPROM
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-CLCC Window, 68-CERQUAD
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA16XL680 - ADAPTER DEVICE FOR MPLAB-ICEAC164024 - ADAPTER PICSTART PLUS 68PLCCAC164022 - MODULE SKT PROMATEII 68PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PIC16C925/926
9.2.2
There are two address formats. The simplest is the
7-bit address format with a R/W bit (Figure 9-7). The
more complex is the 10-bit address with a R/W bit
(Figure 9-8). For 10-bit address format, two bytes must
be transmitted with the first five bits specifying this to be
a 10-bit address.
FIGURE 9-7:
FIGURE 9-8:
FIGURE 9-10:
DS39544A-page 66
S
R/W
ACK
S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
ACK
S
R/W
- START Condition
- Read/Write Pulse
- Acknowledge
SDA
SCL
START Condition
Read/Write pulse
Acknowledge
ADDRESSING I
Condition
S
START
S
MSb
MSB
Slave Address
7-BIT ADDRESS FORMAT
I
FORMAT
DATA TRANSFER WAIT STATE
2
1
C 10-BIT ADDRESS
2
Address
C DEVICES
2
Sent by Slave
= 0 for Write
Acknowledgment
Signal from Receiver
LSb
R/W ACK
7
Sent by
Slave
R/W
8
Preliminary
ACK
9
Byte Complete
Interrupt with Receiver
Wait
State
9.2.3
All data must be transmitted per byte, with no limit to
the number of bytes transmitted per data transfer. After
each byte, the slave-receiver generates an Acknowl-
edge bit (ACK) (see Figure 9-9). When a slave-receiver
doesn’t acknowledge the slave address or received
data, the master must abort the transfer. The slave
must leave SDA high so that the master can generate
the STOP condition (Figure 9-6).
FIGURE 9-9:
If the master is receiving the data (master-receiver), it
generates an Acknowledge signal for each received
byte of data, except for the last byte. To signal the end
of data to the slave-transmitter, the master does not
generate an Acknowledge (Not Acknowledge). The
slave then releases the SDA line so the master can
generate the STOP condition. The master can also
generate the STOP condition during the Acknowledge
pulse for valid termination of data transfer.
If the slave needs to delay the transmission of the next
byte, holding the SCL line low will force the master into
a wait state. Data transfer continues when the slave
releases the SCL line. This allows the slave to move
the received data, or fetch the data it needs to transfer
before allowing the clock to start. This wait state tech-
nique can also be implemented at the bit level,
Figure 9-10. The slave will inherently stretch the clock
when it is a transmitter, but will not when it is a receiver.
The slave will have to clear the SSPCON<4> bit to
enable clock stretching when it is a receiver.
Transmitter
Output by
Output by
Clock Line Held Low while
Interrupts are Serviced
SCL from
Receiver
Master
1
Data
Data
Data
Condition
START
TRANSFER ACKNOWLEDGE
2
S
Acknowledgment
Signal from Receiver
3
1
8
SLAVE-RECEIVER
ACKNOWLEDGE
2001 Microchip Technology Inc.
ACK
9
2
Not Acknowledge
Acknowledge
Condition
STOP
8
Acknowledgment
P
Clock Pulse for
9