ATMEGA32L-8AC Atmel, ATMEGA32L-8AC Datasheet - Page 101
![IC AVR MCU 32K LV 8MHZ COM44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA32L-8AC
Manufacturer Part Number
ATMEGA32L-8AC
Description
IC AVR MCU 32K LV 8MHZ COM44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32L-8AC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA32L-8AC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Phase Correct PWM
Mode
2503Q–AVR–02/11
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the out-
put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP
will result in a constant high or low output (depending on the polarity of the output set by the
COM1x1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). This applies only
if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have
a maximum frequency of f
similar to the OC1A toggle in CTC mode, except the double buffer feature of the output compare
unit is enabled in the fast PWM mode.
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1,2,3,10,
or 11) provides a high resolution phase correct PWM waveform generation option. The phase
correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope
operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to
BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on
the compare match between TCNT1 and OCR1x while upcounting, and set on the compare
match while downcounting. In inverting Output Compare mode, the operation is inverted. The
dual-slope operation has lower maximum operation frequency than single slope operation. How-
ever, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for
motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-bit, 9-bit, or 10-bit, or
defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set
to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM reso-
lution in bits can be calculated by using the following equation:
In phase correct PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1
(WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the
TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock
cycle. The timing diagram for the phase correct PWM mode is shown on
shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1
value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on
the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Inter-
rupt Flag will be set when a compare match occurs.
OC
1
A
= f
f
clk_I/O
OCnxPWM
R
PCPWM
/2 when OCR1A is set to zero (0x0000). This feature is
=
=
log
---------------------------------- -
---------------------------------- -
N
⋅
(
log
(
f
TOP
clk_I/O
1
+
2 ( )
TOP
+
1
)
)
ATmega32(L)
Figure
47. The figure
101
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