ATMEGA32L-8AC Atmel, ATMEGA32L-8AC Datasheet - Page 66
![IC AVR MCU 32K LV 8MHZ COM44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA32L-8AC
Manufacturer Part Number
ATMEGA32L-8AC
Description
IC AVR MCU 32K LV 8MHZ COM44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32L-8AC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA32L-8AC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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External
Interrupts
MCU Control Register
– MCUCR
2503Q–AVR–02/11
The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled,
the interrupts will trigger even if the INT0..2 pins are configured as outputs. This feature provides
a way of generating a software interrupt. The external interrupts can be triggered by a falling or
rising edge or a low level (INT2 is only an edge triggered interrupt). This is set up as indicated in
the specification for the MCU Control Register – MCUCR – and MCU Control and Status Regis-
ter – MCUCSR. When the external interrupt is enabled and is configured as level triggered (only
INT0/INT1), the interrupt will trigger as long as the pin is held low. Note that recognition of falling
or rising edge interrupts on INT0 and INT1 requires the presence of an I/O clock, described in
“Clock Systems and their Distribution” on page
edge interrupt on INT2 are detected asynchronously. This implies that these interrupts can be
used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in
all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. This makes the MCU less sensitive to
noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the
Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the Watchdog Oscilla-
tor is voltage dependent as shown in
wake up if the input has the required level during this sampling or if it is held until the end of the
start-up time. The start-up time is defined by the SUT fuses as described in
Clock Options” on page
disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be
generated. The required level must be held long enough for the MCU to complete the wake up to
trigger the level interrupt.
The MCU Control Register contains control bits for interrupt sense control and general MCU
functions.
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and the corre-
sponding interrupt mask in the GICR are set. The level and edges on the external INT1 pin that
activate the interrupt are defined in
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If
low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt.
Table 34. Interrupt 1 Sense Control
Bit
Read/Write
Initial Value
ISC11
0
0
1
1
ISC10
0
1
0
1
R/W
SE
7
0
Description
The low level of INT1 generates an interrupt request.
Any logical change on INT1 generates an interrupt request.
The falling edge of INT1 generates an interrupt request.
The rising edge of INT1 generates an interrupt request.
SM2
R/W
6
0
24. If the level is sampled twice by the Watchdog Oscillator clock but
SM1
R/W
5
0
Table
“Electrical Characteristics” on page
SM0
R/W
4
0
34. The value on the INT1 pin is sampled before
ISC11
R/W
24. Low level interrupts on INT0/INT1 and the
3
0
ISC10
R/W
2
0
ISC01
R/W
1
0
ATmega32(L)
ISC00
R/W
0
0
287. The MCU will
“System Clock and
MCUCR
66
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