ATMEGA8515-16AC Atmel, ATMEGA8515-16AC Datasheet - Page 91
ATMEGA8515-16AC
Manufacturer Part Number
ATMEGA8515-16AC
Description
IC AVR MCU 8K 16MHZ COM 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8515-16AC
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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8-bit Timer/Counter
Register Description
Timer/Counter Control
Register – TCCR0
2512K–AVR–01/10
• Bit 7 – FOC0: Force Output Compare
The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However,
for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is
written when operating in PWM mode. When writing a logical one to the FOC0 bit, an
immediate Compare Match is forced on the waveform generation unit. The OC0 output
is changed according to its COM01:0 bits setting. Note that the FOC0 bit is implemented
as a strobe. Therefore it is the value present in the COM01:0 bits that determines the
effect of the forced compare.
A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode
using OCR0 as TOP.
The FOC0 bit is always read as zero.
• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum
(TOP) counter value, and what type of waveform generation to be used. Modes of oper-
ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare
Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table
44 and “Modes of Operation” on page 85.
Table 44. Waveform Generation Mode Bit Description
Note:
• Bit 5:4 – COM01:0: Compare Match Output Mode
These bits control the Output Compare pin (OC0) behavior. If one or both of the
COM01:0 bits are set, the OC0 output overrides the normal port functionality of the I/O
pin it is connected to. However, note that the Data Direction Register (DDR) bit corre-
sponding to the OC0 pin must be set in order to enable the output driver.
Bit
Read/Write
Initial Value
Mode
0
1
2
3
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-
WGM01
(CTC0)
initions. However, the functionality and location of these bits are compatible with
previous versions of the timer.
0
0
1
1
FOC0
W
7
0
WGM00
(PWM0)
WGM00
R/W
0
1
0
1
6
0
COM01
Timer/Counter Mode
of Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
R/W
5
0
COM00
R/W
4
0
WGM01
R/W
3
0
(1)
TOP
0xFF
0xFF
OCR0
0xFF
CS02
R/W
ATmega8515(L)
2
0
Update of
OCR0 at
Immediate
TOP
Immediate
BOTTOM
CS01
R/W
1
0
CS00
R/W
0
0
TOV0 Flag
Set on
MAX
BOTTOM
MAX
MAX
TCCR0
91
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