ATMEGA162L-8AI Atmel, ATMEGA162L-8AI Datasheet - Page 152

• Manufacturer Part Number: ATMEGA162L-8AI
• Description: IC MCU AVR 16K 3V 8MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162L-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Timer/Counter Interrupt Mask
Register – TIMSK
152
ATmega162(V/U/L)
•
•
•
• Bit 4 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is
executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2 bit is set in
the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 2 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if
an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the
Timer/Counter Interrupt Flag Register – TIFR.
Bit
Read/Write
Initial Value
no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1
pin.
Description of wake up from Power-save or Extended Standby mode when the
Timer is clocked asynchronously: When the interrupt condition is met, the wake up
process is started on the following cycle of the timer clock, that is, the Timer is
always advanced by at least one before the processor can read the counter value.
After wake-up, the MCU is halted for four cycles, it executes the interrupt routine,
and resumes execution from the instruction following SLEEP.
Reading of the TCNT2 Register shortly after wake-up from Power-save may give an
incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading
TCNT2 must be done through a register synchronized to the internal I/O clock
domain. Synchronization takes place for every rising TOSC1 edge. When waking up
from Power-save mode, and the I/O clock (clk
read as the previous value (before entering sleep) until the next rising TOSC1 edge.
The phase of the TOSC clock after waking up from Power-save mode is essentially
unpredictable, as it depends on the wake-up time. The recommended procedure for
reading TCNT2 is thus as follows:
1. Write any value to either of the registers OCR2 or TCCR2.
2. Wait for the corresponding Update Busy Flag to be cleared.
3. Read TCNT2.
During asynchronous operation, the synchronization of the interrupt flags for the
Asynchronous Timer takes three processor cycles plus one timer cycle. The Timer
is therefore advanced by at least one before the processor can read the Timer value
causing the setting of the interrupt flag. The output compare pin is changed on the
Timer clock and is not synchronized to the processor clock.
TOIE1
R/W
7
0
OCIE1A
R/W
6
0
OCIE1B
R/W
5
0
OCIE2
R/W
4
0
TICIE1
R/W
3
0
I/O
) again becomes active, TCNT2 will
TOIE2
R/W
2
0
TOIE0
R/W
1
0
OCIE0
R/W
0
0
2513C–AVR–09/02
TIMSK