ATMEGA169V-8MI Atmel, ATMEGA169V-8MI Datasheet - Page 350
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ATMEGA169V-8MI
Manufacturer Part Number
ATMEGA169V-8MI
Description
IC MCU AVR 16K 1.8V 1MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA169V-8MI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
For Use With
ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA169V-1MI
ATMEGA169V-1MI
ATMEGA169V-1MI
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- Download datasheet (4Mb)
ATmega169 Rev C
350
ATmega169/V
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6. Interrupts may be lost when writing the timer registers in the asynchronous
5. High Current Consumption In Power Down when JTAGEN is Programmed
4. LCD Contrast Control
3. Some Data Combinations Can Result in Dim Segments on the LCD
2. LCD Current Consumption
1. IDCODE masks data from TDI input
Interrupts may be lost when writing the timer registers in the asynchronous timer
High Current Consumption In Power Down when JTAGEN is Programmed
LCD Contrast Control
Some Data Combinations Can Result in Dim Segments on the LCD
LCD Current Consumption
IDCODE masks data from TDI input
timer
If one of the timer registers which is synchronized to the asynchronous timer2 clock
is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.
Problem Fix/Workaround
Always check that the Timer2 Timer/Counter register, TCNT2, does not have the
value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare
Register, OCR2.
The input buffer on TDO (PF6) is always enabled and the pull-up is always disabled
when JTAG is programmed. This can leave the output floating.
Problem Fix/Workaround
Add external pull-up to PF6.
Unprogram the JTAGEN Fuse before shipping out the end product.
The contrast control is not working properly when using synchronous clock (chip
clock) to obtain an LCD clock, and the chip clock is 125 kHz or faster.
Problem Fix/Workaround
Use a low chip clock frequency (32 kHz) or apply an external voltage to the LCD-
CAP pin.
All segments connected to a common plane might be dimmed (lower contrast) when
a certain combination of data is displayed.
Problem Fix/Workaround
Default waveform: If there are any unused segment pins, loading one of these with a
1 nF capacitor and always write ‘0’ to this segment eliminates the problem.
Low power waveform: Add a 1 nF capacitor to each common pin.
In an interval where V
current consumption is up to three times higher than expected. This will only be an
issue in Power-save mode with the LCD running as the LCD current is negligible
compared to the overall power consumption in all other modes of operation.
Problem Fix/Workaround
No known workaround.
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices
are replaced by all-ones during Update-DR.
CC
is within the range VLCD -0.2V to VLCD + 0.4V, the LCD
2514P–AVR–07/06
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