PIC16LF74T-I/ML Microchip Technology, PIC16LF74T-I/ML Datasheet - Page 18

• Manufacturer Part Number: PIC16LF74T-I/ML
• Description: IC MCU FLASH 4KX14 A/D 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF74T-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16F7X
2.2.2
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
DS30325B-page 16
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend:
Note
Address
Bank 0
(4)
(4)
(4)
(4)
(5)
(5)
(1,4)
(4)
1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter during branches ( CALL or GOTO ).
SPECIAL FUNCTION REGISTERS
Name
SPECIAL FUNCTION REGISTER SUMMARY
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address Pointer
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Timer2 Module Register
Synchronous Serial Port Receive Buffer/Transmit Register
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
USART Transmit Data Register
USART Receive Data Register
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
A/D Result Register Byte
PSPIF
ADCS1
WCOL
SPEN
Bit 7
GIE
IRP
—
—
—
—
—
—
—
—
(3)
TOUTPS3 TOUTPS2
SSPOV
ADCS0
Bit 6
PEIE
ADIF
RP1
RX9
—
—
—
—
—
—
—
PORTA Data Latch when written: PORTA pins when read
T1CKPS1
TMR0IE
SSPEN
CCP1X
CCP2X
SREN
CHS2
RCIF
Bit 5
RP0
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
T1CKPS0
TOUTPS
CCP1Y
CCP2Y
CREN
CHS1
INTE
Bit 4
TXIF
CKP
TO
—
—
T1OSCEN T1SYNC
TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
CCP1M3
CCP2M3
SSPM3
SSPIF
CHS0
RBIE
Bit 3
PD
—
—
—
CCP1M2
CCP2M2
TMR0IF
CCP1IF
SSPM2
DONE
FERR
Bit 2
RE2
GO/
—
Z
TMR1CS
CCP1M1
CCP2M1
TMR2IF
SSPM1
OERR
INTF
Bit 1
RE1
DC
—
—
 2002 Microchip Technology Inc.
TMR1ON
CCP1M0
CCP2M0
TMR1IF
CCP2IF
SSPM0
ADON
RX9D
Bit 0
RBIF
RE0
C
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--0x 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- -xxx
---0 0000
0000 000x
0000 0000
---- ---0
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
-000 0000
xxxx xxxx 64, 68, 96
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 -00x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
0000 00-0
Value on:
POR,
BOR
on page
Details
27, 96
45, 96
26, 96
19, 96
27, 96
32, 96
34, 96
35, 96
36, 96
39, 96
26, 96
21, 96
23, 96
24, 96
50, 96
50, 96
47, 96
52, 96
52, 96
61, 96
56, 96
56, 96
54, 96
70, 96
74, 96
76, 96
58, 96
58, 96
54, 96
88, 96
83, 96