PIC16LF74T-I/ML Microchip Technology, PIC16LF74T-I/ML Datasheet - Page 70

• Manufacturer Part Number: PIC16LF74T-I/ML
• Description: IC MCU FLASH 4KX14 A/D 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF74T-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16F7X
9.3.2
Master mode of operation is supported in firmware
using interrupt generation on the detection of the
START and STOP conditions. The STOP (P) and
START (S) bits are cleared from a RESET or when the
SSP module is disabled. The STOP (P) and START (S)
bits will toggle based on the START and STOP condi-
tions. Control of the I
bit is set, or the bus is IDLE and both the S and P bits
are clear.
In Master mode, the SCL and SDA lines are manipu-
lated by clearing the corresponding TRISC<4:3> bit(s).
The output level is always low, irrespective of the
value(s) in PORTC<4:3>. So when transmitting data, a
’1’ data bit must have the TRISC<4> bit set (input) and
a ’0’ data bit must have the TRISC<4> bit cleared (out-
put). The same scenario is true for the SCL line with the
TRISC<3> bit. Pull-up resistors must be provided
externally to the SCL and SDA pins for proper opera-
tion of the I
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt will occur if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
Slave mode IDLE (SSPM3:SSPM0 = 1011), or with the
Slave active. When both Master and Slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
TABLE 9-3:
DS30325B-page 68
0Bh, 8Bh,
10Bh,18Bh
0Ch
8Ch
13h
93h
14h
94h
87h
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ’0’. Shaded cells are not used by SSP module in I
Note 1: PSPIF and PSPIE are reserved on the PIC16F73/76; always maintain these bits clear.
Address
2: Maintain these bits clear in I
2
MASTER MODE
C module.
INTCON
PIR1
PIE1
SSPBUF
SSPADD
SSPCON
SSPSTAT
TRISC
Name
REGISTERS ASSOCIATED WITH I
2
C bus may be taken when the P
Synchronous Serial Port Receive Buffer/Transmit Register
Synchronous Serial Port (I
PORTC Data Direction Register
PSPIF
PSPIE
SMP
WCOL
Bit 7
GIE
(2)
(1)
(1)
SSPOV SSPEN
CKE
ADIE
Bit 6
PEIE
ADIF
2
C mode.
(2)
TMR0IE
RCIE
RCIF
Bit 5
D/A
2
C mode) Address Register
INTE
Bit 4
TXIF
TXIE
CKP
P
SSPM3 SSPM2 SSPM1 SSPM0
SSPIF CCP1IF TMR2IF TMR1IF
SSPIE CCP1IE TMR2IE TMR1IE
2
RBIE
Bit 3
C OPERATION
S
9.3.3
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions, allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the SSP module is disabled. The STOP (P) and
START (S) bits will toggle based on the START and
STOP conditions. Control of the I
when bit P (SSPSTAT<4>) is set, or the bus is IDLE
and both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
In Multi-Master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
• Address Transfer
• Data Transfer
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address trans-
fer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be gener-
ated. If arbitration was lost during the data transfer
stage, the device will need to retransfer the data at a
later time.
TMR0IF
Bit 2
R/W
MULTI-MASTER MODE
Bit 1
INTF
UA
RBIF
Bit 0
BF
 2002 Microchip Technology Inc.
0000 000x
0000 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
1111 1111
Value on:
POR,
BOR
2
C bus may be taken
0000 0000
0000 0000
0000 000u
uuuu uuuu
0000 0000
0000 0000
0000 0000
1111 1111
Value on
RESETS
all other
2
C mode.