PIC18F4539T-E/ML Microchip Technology, PIC18F4539T-E/ML Datasheet - Page 80

• Manufacturer Part Number: PIC18F4539T-E/ML
• Description: IC PIC MCU FLASH 12KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4539T-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 24KB (12K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1408 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1408 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18FXX39
8.4
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are two Peripheral Inter-
rupt Priority registers (IPR1, IPR2). The operation of
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
For PIC18FXX39 devices, the Motor Control kernel
requires that the Timer2 to PR2 match interrupt be the
only high priority interrupt. Failure to do this may result
in unpredictable operation of the kernel or the entire
microcontroller.
REGISTER 8-8:
DS30485A-page 78
IPR Registers
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
bit 7
PSPIP
1 = High priority
0 = Low priority
ADIP
1 = High priority
0 = Low priority
RCIP
1 = High priority
0 = Low priority
TXIP
1 = High priority
0 = Low priority
SSPIP
1 = High priority
0 = Low priority
Unimplemented: Read as ‘1’
TMR2IP
1 = High priority
0 = Low priority
TMR1IP
1 = High priority
0 = Low priority
PSPIP
Legend:
R = Readable bit
- n = Value at POR
R/W-1
Note 1: This bit is reserved on PIC18F2X39 devices.
(2)
(2)
(2)
(1,2)
(2)
(1,2)
: USART Transmit Interrupt Priority bit
: A/D Converter Interrupt Priority bit
: USART Receive Interrupt Priority bit
(3)
(2)
2: Maintain this bit cleared (= 0).
3: This bit is reserved for use by the ProMPT kernel; always maintain this bit set (= 1).
: Master Synchronous Serial Port Interrupt Priority bit
: Parallel Slave Port Read/Write Interrupt Priority bit
: TMR2 to PR2 Match Interrupt Priority bit
: TMR1 Overflow Interrupt Priority bit
ADIP
R/W-1
(2)
RCIP
R/W-1
Preliminary
W = Writable bit
‘1’ = Bit is set
(2)
TXIP
R/W-1
In practical terms, this means:
• Interrupt priority levels are enabled (IPEN = 1);
• High priority interrupts are enabled
• Timer2 interrupt is enabled and set as high priority
• all other interrupts are disabled (INTCON or PIR
(INTCON<7> = 1);
(PIE1<1> and IPR<1> = 1); and
bits = 0), or set as low priority (IPR bits = 0).
Note:
(2)
SSPIP
R/W-1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Configuring the interrupts is automatically
done
ProMPT_Init(PWMfrequency). It is the
user’s responsibility to make certain that
this method is called at the very beginning
of the application.
(2)
by
U-1
—
 2002 Microchip Technology Inc.
the
API
TMR2IP
x = Bit is unknown
R/W-1
method
(3)
TMR1IP
R/W-1
void
bit 0
(2)