PIC18F4539T-E/ML Microchip Technology, PIC18F4539T-E/ML Datasheet - Page 83

• Manufacturer Part Number: PIC18F4539T-E/ML
• Description: IC PIC MCU FLASH 12KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4539T-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 24KB (12K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1408 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1408 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.6
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge triggered: either rising, if the
corresponding INTEDGx bit is set in the INTCON2 reg-
ister, or falling, if the INTEDGx bit is clear. When a valid
edge appears on the RBx/INTx pin, the corresponding
flag bit INTxF is set. This interrupt can be disabled by
clearing the corresponding enable bit INTxE. Flag bit
INTxF must be cleared in software in the Interrupt Ser-
vice Routine before re-enabling the interrupt. All exter-
nal interrupts (INT0, INT1 and INT2) can wake-up the
processor from SLEEP, if bit INTxE was set prior to
going into SLEEP. If the global interrupt enable bit GIE
is set, the processor will branch to the interrupt vector
following wake-up.
The INT0 interrupt is always configured as a high prior-
ity interrupt, and cannot be reconfigured. Interrupt pri-
ority for INT1 and INT2 is determined by the value
contained in the interrupt priority bits, INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>).
Because it is always configured as a high priority inter-
rupt, INT0 cannot be used in conjunction with the
ProMPT
(INTCON<4> = 0). Failure to do this may result in
erratic operation of the motor control.
EXAMPLE 8-1:
 2002 Microchip Technology Inc.
MOVWF
MOVFF
MOVFF
;
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
INT0 Interrupt
W_TEMP
STATUS, STATUS_TEMP
BSR,
BSR_TEMP,
W_TEMP,
STATUS_TEMP,STATUS
kernel;
BSR_TEMP
it
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
must
BSR
W
always
be
disabled
Preliminary
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
8.7
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh → 00h) will set flag bit TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L regis-
ter pair (FFFFh → 0000h) will set flag bit TMR0IF. The
interrupt can be enabled or disabled by setting or
clearing enable bit TMR0IE (INTCON<5>). Interrupt
priority for Timer0 is determined by the value contained
in the interrupt priority bit TMR0IP (INTCON2<2>). See
Section 10.0 for further details on the Timer0 module.
8.8
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled or dis-
abled by setting or clearing the enable bit RBIE
(INTCON<3>). Interrupt priority for PORTB interrupt-
on-change is determined by the value contained in the
interrupt priority bit RBIP (INTCON2<0>).
8.9
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, STATUS and BSR regis-
ters are saved on the fast return stack. If a fast return
from interrupt is not used (see Section 4.3), the user
may need to save the WREG, STATUS and BSR regis-
ters in software. Depending on the user’s application,
other registers may also need to be saved. Example 8-1
saves and restores the WREG, STATUS and BSR
registers during an Interrupt Service Routine.
TMR0 Interrupt
PORTB Interrupt-on-Change
Context Saving During Interrupts
PIC18FXX39
DS30485A-page 81