ATMEGA48-20MI Atmel, ATMEGA48-20MI Datasheet - Page 73

• Manufacturer Part Number: ATMEGA48-20MI
• Description: IC AVR MCU 4K 5V 20MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA48-20MI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA48-24MI; ATMEGA48-24MI

2545S–AVR–07/10
Figure 13-3. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in
the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
Figure 13-4. Synchronization when Reading a Software Assigned Pin Value
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define
the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin
values are read back again, but as previously discussed, a nop instruction is included to be able
to read back the value recently assigned to some of the pins.
INSTRUCTIONS
INSTRUCTIONS
SYSTEM CLK
SYSTEM CLK
SYNC LATCH
SYNC LATCH
Figure
13-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of
PINxn
PINxn
r17
r16
r17
out PORTx, r16
XXX
t
pd, max
0x00
0x00
XXX
nop
t
pd
t
0xFF
pd, min
ATmega48/88/168
in r17, PINx
in r17, PINx
0xFF
0xFF
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