ATAM893T-TKS Atmel, ATAM893T-TKS Datasheet - Page 35

• Manufacturer Part Number: ATAM893T-TKS
• Description: IC MON TIRE-PRESS ATARX9X SER
• Manufacturer: Atmel
• Series: MARC4r

Specifications of ATAM893T-TKS

• Core Processor: MARC4
• Core Size: 4-Bit
• Speed: 4MHz
• Connectivity: SSI (2-Wire, 3 Wire)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 16
• Ram Size: 256 x 4
• Voltage - Supply (vcc/vdd): 1.8 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (5.3mm Width), 20-SO, 20-SOEIAJ
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

5.3.1.2
5.3.1.3
4680C–4BMCU–01/05
Timer 1 Control Register 2 (T1C2)
Watchdog Control Register (WDC)
Bit 3 = MSB, Bit 0 = LSB
Bit 3 = MSB, Bit 0 = LSB
Both these bits control the time interval for the watchdog reset.
T1C2
T1BP
T1CS
T1IM
WDC
WDL
WDR
WDT1
WDT0
WatchDog Lock mode
WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit
WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no
WatchDog Run and stop mode
WDR = 1, the watchdog is stopped/disabled
WDR = 0, the watchdog is active/enabled
WatchDog Time 1
WatchDog Time 0
Bit 3
–
Timer 1 SUBCL ByPassed
T1BP = 1, TIOUT = T1MUX
T1BP = 0, T1OUT = SUBCL
Timer 1 input Clock Select
T1CS = 1, CL1 = SUBCL (see
T1CS = 0, CL1 = SYSCL (see
Timer 1 Interrupt Mask
T1IM = 1, disables Timer 1 interrupt
T1IM = 0, enables Timer 1 interrupt
Bit 3
WDL
effect. After the WDL-bit is cleared, the watchdog is active until a system
reset or power-on reset occurs.
Bit 2
T1BP
Bit 2
WDR
Bit 1
T1CS
Bit 1
WDT1
Figure 5-8 on page
Figure 5-8 on page
Bit 0
T1IM
Bit 0
WDT0
Address: ’7’hex - Subaddress: ’9’hex
Reset value: x111b
Address: ’7’hex - Subaddress: ’A’hex
Reset value: 1111b
33)
33)
ATAM893-D
35