ATAM893T-TKS Atmel, ATAM893T-TKS Datasheet - Page 77

• Manufacturer Part Number: ATAM893T-TKS
• Description: IC MON TIRE-PRESS ATARX9X SER
• Manufacturer: Atmel
• Series: MARC4r

Specifications of ATAM893T-TKS

• Core Processor: MARC4
• Core Size: 4-Bit
• Speed: 4MHz
• Connectivity: SSI (2-Wire, 3 Wire)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 16
• Ram Size: 256 x 4
• Voltage - Supply (vcc/vdd): 1.8 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (5.3mm Width), 20-SO, 20-SOEIAJ
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

4680C–4BMCU–01/05
Combination Mode 6: FSK Modulation
SSI mode 1:
Timer 3 mode 8:
The two compare registers are used to generate two varied time intervals. The SSI data output
selects which compare register is used for the output frequency generation. A '0'-level at the SSI
data output enables the compare register 1 and a '1'-level enables the compare register 2. The
compare and compare mode registers must be programmed to generate the two frequencies via
the output toggle flip-lop. The SSI can be supplied with the toggle signal of Timer 2 or any other
clock source. The Timer 3 counter is driven by an internal or external clock source.
Figure 5-55. FSK Modulation 1
Combination Mode 7: Pulse-width Modulation (PWM)
SSI mode 1:
Timer 3 mode 9:
The two compare registers are used to generate two varied time intervals. The SSI data output
selects which compare register is used for the output pulse generation. In this mode, both com-
pare and compare mode registers must be programmed to generate the two pulse width. It is
also useful to enable the single-action mode for extreme duty cycles. Timer 2 is used as baud-
rate generator and for the triggered restart of Timer 3. The SSI must be supplied with the toggle
signal of Timer 2. The counter is driven by an internal or external clock source.
Figure 5-56. Pulse-width Modulation
Counter 3
TOG2
CM31
CM32
SCO
T3O
T3R
SIR
Counter 3
SO
CM31
CM32
T3R
T3O
SO
0 0 0 0 0 0 0 0 0
0 1 2 3 4 0 1 2 3 4 0 1 2 3
8-bit shift register internal data output (SO) to the Timer 3
FSK modulation with shift register data (SO)
8-bit shift register internal data output (SO) to the Timer 3
Pulse-width modulation with the shift register data (SO)
0
0 0 0 0
0
0
0 0 0 0 0 1 2 3 4 5 6 7 8 910 11 12 13 14 15 0 1 2 3 4 5
4 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 3
1
1
6 7 8
0
ATAM893-D
9 11 12
10
13
14
0
15
4 0
0
1
1
2 3
1
4
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