DSPIC30F6014A-20I/PT Microchip Technology, DSPIC30F6014A-20I/PT Datasheet - Page 125
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DSPIC30F6014A-20I/PT
Manufacturer Part Number
DSPIC30F6014A-20I/PT
Description
IC DSPIC MCU/DSP 144K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F6011A-30IPT.pdf
(8 pages)
3.DSPIC30F6011A-20IPT.pdf
(238 pages)
Specifications of DSPIC30F6014A-20I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
DSPIC30F6014A20IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6014A-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F6011A-30IPT PDF datasheet #2
- DSPIC30F6011A-20IPT PDF datasheet #3
- Current page: 125 of 238
- Download datasheet (4Mb)
18.0
18.1
The dsPIC30F Data Converter Interface (DCI) module
allows simple interfacing of devices, such as audio
coder/decoders (Codecs), A/D converters and D/A
converters. The following interfaces are supported:
• Framed Synchronous Serial Transfer (Single or
• Inter-IC Sound (I
• AC-Link Compliant mode
The DCI module provides the following general
features:
• Programmable word size up to 16 bits
• Support for up to 16 time slots, for a maximum
• Data buffering for up to 4 samples without CPU
18.2
There are four I/O pins associated with the module.
When enabled, the module controls the data direction
of each of the four pins.
18.2.1
The CSCK pin provides the serial clock for the DCI
module. The CSCK pin may be configured as an input
or output using the CSCKD control bit in the DCICON2
SFR. When configured as an output, the serial clock is
provided by the dsPIC30F. When configured as an
input, the serial clock must be provided by an external
device.
18.2.2
The serial data output (CSDO) pin is configured as an
output only pin when the module is enabled. The
CSDO pin drives the serial bus whenever data is to be
transmitted. The CSDO pin is tri-stated or driven to ‘0’
during CSCK periods when data is not transmitted,
depending on the state of the CSDOM control bit. This
allows other devices to place data on the serial bus
during transmission periods not used by the DCI
module.
© 2005 Microchip Technology Inc.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046).
Multi-Channel)
frame size of 256 bits
overhead
DATA CONVERTER
INTERFACE (DCI) MODULE
Module Introduction
Module I/O Pins
CSCK PIN
CSDO PIN
2
S) Interface
dsPIC30F6011A/6012A/6013A/6014A
Preliminary
18.2.3
The serial data input (CSDI) pin is configured as an
input only pin when the module is enabled.
18.2.3.1
The Codec Frame Synchronization (COFS) pin is used
to synchronize data transfers that occur on the CSDO
and CSDI pins. The COFS pin may be configured as an
input or an output. The data direction for the COFS pin
is determined by the COFSD control bit in the
DCICON1 register.
The DCI module accesses the shadow registers while
the CPU is in the process of accessing the memory
mapped buffer registers.
18.2.4
Data values are always stored left justified in the buff-
ers since most Codec data is represented as a signed
2’s complement fractional number. If the received word
length is less than 16 bits, the unused LSbs in the
receive buffer registers are set to ‘0’ by the module. If
the transmitted word length is less than 16 bits, the
unused LSbs in the transmit buffer register are ignored
by the module. The word length setup is described in
subsequent sections of this document.
18.2.5
The DCI module has a 16-bit shift register for shifting
serial data in and out of the module. Data is shifted in/
out of the shift register MSb first, since audio PCM data
is transmitted in signed 2’s complement format.
18.2.6
The DCI module contains a buffer control unit for trans-
ferring data between the shadow buffer memory and
the serial shift register. The buffer control unit is a sim-
ple 2-bit address counter that points to word locations
in the shadow buffer memory. For the receive memory
space (high address portion of DCI buffer memory), the
address counter is concatenated with a ‘0’ in the MSb
location to form a 3-bit address. For the transmit mem-
ory space (high portion of DCI buffer memory), the
address counter is concatenated with a ‘1’ in the MSb
location.
Note:
CSDI PIN
BUFFER DATA ALIGNMENT
TRANSMIT/RECEIVE SHIFT
REGISTER
DCI BUFFER CONTROL
The DCI buffer control unit always
accesses the same relative location in the
transmit and receive buffers, so only one
address counter is provided.
COFS PIN
DS70143B-page 123
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