DSPIC30F6014A-20I/PT Microchip Technology, DSPIC30F6014A-20I/PT Datasheet - Page 60
DSPIC30F6014A-20I/PT
Manufacturer Part Number
DSPIC30F6014A-20I/PT
Description
IC DSPIC MCU/DSP 144K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F6011A-30IPT.pdf
(8 pages)
3.DSPIC30F6011A-20IPT.pdf
(238 pages)
Specifications of DSPIC30F6014A-20I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
DSPIC30F6014A20IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6014A-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F6011A-30IPT PDF datasheet #2
- DSPIC30F6011A-20IPT PDF datasheet #3
- Current page: 60 of 238
- Download datasheet (4Mb)
dsPIC30F6011A/6012A/6013A/6014A
7.2
7.2.1
In order to erase a block of data EEPROM, the
NVMADRU and NVMADR registers must initially point
to the block of memory to be erased. Configure
NVMCON for erasing a block of data EEPROM, and
set the ERASE and WREN bits in the NVMCON
register. Setting the WR bit initiates the erase as
shown in Example 7-2.
EXAMPLE 7-2:
7.2.2
The TBLPAG and NVMADR registers must point to the
block. Select erase a block of data Flash, and set the
ERASE and WREN bits in the NVMCON register. Set-
ting the WR bit initiates the erase as shown in
Example 7-3.
EXAMPLE 7-3:
DS70143B-page 58
; Select data EEPROM block, ERASE, WREN bits
; Start erase cycle by setting WR after writing key sequence
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete
; Select data EEPROM word, ERASE, WREN bits
; Start erase cycle by setting WR after writing key sequence
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete
MOV
MOV
DISI
MOV
MOV
MOV
MOV
BSET
MOV
MOV
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
NOP
NOP
Erasing Data EEPROM
ERASING A BLOCK OF DATA
EEPROM
ERASING A WORD OF DATA
EEPROM
#0x4045,W0
W0
#5
#0x55,W0
W0
#0xAA,W1
W1
NVMCON,#WR
#0x4044,W0
W0
#5
#0x55,W0
W0
#0xAA,W1
W1
NVMCON,#WR
,
,
,
,
,
,
NVMCON
NVMKEY
NVMKEY
NVMCON
NVMKEY
NVMKEY
DATA EEPROM BLOCK ERASE
DATA EEPROM WORD ERASE
; Initialize NVMCON SFR
; Block all interrupts with priority <7 for
; next 5 instructions
;
; Write the 0x55 key
;
; Write the 0xAA key
; Initiate erase sequence
Preliminary
; Block all interrupts with priority <7 for
; next 5 instructions
;
; Write the 0x55 key
;
; Write the 0xAA key
; Initiate erase sequence
© 2005 Microchip Technology Inc.
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