DSPIC30F4013T-20I/PT Microchip Technology, DSPIC30F4013T-20I/PT Datasheet - Page 211

• Manufacturer Part Number: DSPIC30F4013T-20I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013T-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• For Use With: AC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: DSPIC30F4013T20IP

INDEX
Numerics
12-bit Analog-to-Digital Converter (A/D) Module .............. 125
A
A/D .................................................................................... 125
AC Characteristics ............................................................ 175
AC Temperature and Voltage Specifications .................... 175
AC-Link Mode Operation .................................................. 122
Address Generator Units .................................................... 35
Alternate Vector Table ........................................................ 59
Analog-to-Digital Converter. See A/D.
Assembler
Automatic Clock Stretch...................................................... 92
B
Bandgap Start-up Time
Barrel Shifter ....................................................................... 21
Bit-Reversed Addressing .................................................... 38
Block Diagrams
 2004 Microchip Technology Inc.
Aborting a Conversion .............................................. 127
ADCHS Register ....................................................... 125
ADCON1 Register..................................................... 125
ADCON2 Register..................................................... 125
ADCON3 Register..................................................... 125
ADCSSL Register ..................................................... 125
ADPCFG Register..................................................... 125
Configuring Analog Port Pins.............................. 52, 129
Connection Considerations....................................... 129
Conversion Operation ............................................... 126
Effects of a Reset...................................................... 128
Operation During CPU Idle Mode ............................. 128
Operation During CPU Sleep Mode.......................... 128
Output Formats ......................................................... 128
Power-down Modes .................................................. 128
Programming the Sample Trigger............................. 127
Register Map............................................................. 130
Result Buffer ............................................................. 126
Sampling Requirements............................................ 127
Selecting the Conversion Clock ................................ 127
Selecting the Conversion Sequence......................... 126
Load Conditions ........................................................ 175
16-bit Mode ............................................................... 122
20-bit Mode ............................................................... 123
MPASM Assembler................................................... 157
During 10-bit Addressing (STREN = 1)....................... 92
During 7-bit Addressing (STREN = 1)......................... 92
Receive Mode ............................................................. 92
Transmit Mode ............................................................ 92
Requirements............................................................ 182
Timing Characteristics .............................................. 182
Example ...................................................................... 38
Implementation ........................................................... 38
Modifier Values Table ................................................. 39
Sequence Table (16-Entry)......................................... 39
12-bit A/D Functional ................................................ 125
16-bit Timer1 Module .................................................. 63
16-bit Timer2............................................................... 69
16-bit Timer3............................................................... 69
16-bit Timer4............................................................... 74
16-bit Timer5............................................................... 74
32-bit Timer2/3............................................................ 68
32-bit Timer4/5............................................................ 73
CAN Buffers and Protocol Engine............................. 106
Advance Information
BOR Characteristics ......................................................... 174
BOR. See Brown-out Reset.
Brown-out Reset
C
C Compilers
CAN Module ..................................................................... 105
CLKOUT and I/O Timing
Code Examples
Code Protection ................................................................ 131
Control Registers ................................................................ 42
Core Architecture
CPU Architecture Overview ................................................ 13
D
Data Accumulators and Adder/Subtractor .......................... 19
dsPIC30F3014/4013
DCI Module............................................................... 116
Dedicated Port Structure ............................................ 51
DSP Engine ................................................................ 18
dsPIC30F3014.............................................................. 9
dsPIC30F4013............................................................ 10
External Power-on Reset Circuit .............................. 143
I
Input Capture Mode.................................................... 77
Oscillator System...................................................... 133
Output Compare Mode ............................................... 81
Reset System ........................................................... 141
Shared Port Structure................................................. 52
SPI.............................................................................. 86
SPI Master/Slave Connection..................................... 86
UART Receiver........................................................... 98
UART Transmitter....................................................... 97
Characteristics.......................................................... 173
Timing Requirements ............................................... 182
MPLAB C17.............................................................. 158
MPLAB C18.............................................................. 158
MPLAB C30.............................................................. 158
Baud Rate Setting .................................................... 110
CAN1 Register Map.................................................. 112
Frame Types ............................................................ 105
I/O Timing Characteristics ........................................ 199
I/O Timing Requirements.......................................... 199
Message Reception.................................................. 108
Message Transmission............................................. 109
Modes of Operation .................................................. 107
Overview................................................................... 105
Characteristics.......................................................... 180
Requirements ........................................................... 180
Data EEPROM Block Erase ....................................... 48
Data EEPROM Block Write ........................................ 50
Data EEPROM Read.................................................. 47
Data EEPROM Word Erase ....................................... 48
Data EEPROM Word Write ........................................ 49
Erasing a Row of Program Memory ........................... 43
Initiating a Programming Sequence ........................... 44
Loading Write Latches................................................ 44
NVMADR .................................................................... 42
NVMADRU ................................................................. 42
NVMCON.................................................................... 42
NVMKEY .................................................................... 42
Overview..................................................................... 13
Data Space Write Saturation ...................................... 21
Overflow and Saturation ............................................. 19
Round Logic ............................................................... 20
Write Back .................................................................. 20
2
C .............................................................................. 90
DS70138C-page 209