DSPIC30F4013T-20I/PT Microchip Technology, DSPIC30F4013T-20I/PT Datasheet - Page 213

• Manufacturer Part Number: DSPIC30F4013T-20I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013T-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• For Use With: AC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: DSPIC30F4013T20IP

F
Fast Context Saving............................................................ 60
Flash Program Memory ...................................................... 41
I
I/O Pin Specifications
I/O Ports .............................................................................. 51
I
I
I
I
I
I
Idle Current (I
In-Circuit Serial Programming (ICSP) ......................... 41, 131
Input Capture (CAPX) Timing Characteristics .................. 185
Input Capture Module ......................................................... 77
Input Capture Operation During Sleep and Idle Modes ...... 78
Input Capture Timing Requirements ................................. 185
Input Change Notification Module ....................................... 54
 2004 Microchip Technology Inc.
2
2
2
2
2
2
C 10-bit Slave Mode Operation ........................................ 91
C 7-bit Slave Mode Operation .......................................... 91
C Master Mode Operation ................................................ 93
C Master Mode Support ................................................... 93
C Module .......................................................................... 89
S Mode Operation .......................................................... 123
Input .......................................................................... 171
Output ....................................................................... 172
Parallel (PIO) .............................................................. 51
Reception.................................................................... 92
Transmission............................................................... 91
Reception.................................................................... 91
Transmission............................................................... 91
Baud Rate Generator.................................................. 94
Clock Arbitration.......................................................... 94
Multi-Master Communication, Bus Collision
Reception.................................................................... 94
Transmission............................................................... 93
Addresses ................................................................... 91
Bus Data Timing Characteristics
Bus Data Timing Requirements
Bus Start/Stop Bits Timing Characteristics
General Call Address Support .................................... 93
Interrupts..................................................................... 93
IPMI Support ............................................................... 93
Operating Function Description .................................. 89
Operation During CPU Sleep and Idle Modes ............ 94
Pin Configuration ........................................................ 89
Programmer’s Model................................................... 89
Register Map............................................................... 95
Registers..................................................................... 89
Slope Control .............................................................. 93
Software Controlled Clock Stretching (STREN = 1).... 92
Various Modes ............................................................ 89
Data Justification....................................................... 123
Frame and Data Word Length Selection................... 123
Interrupts..................................................................... 78
Register Map............................................................... 79
CPU Idle Mode............................................................ 78
CPU Sleep Mode ........................................................ 78
dsPIC30F3014 Register Map (Bits 15-8) .................... 54
dsPIC30F3014 Register Map (Bits 7-0) ...................... 54
dsPIC30F4013 Register Map (Bits 15-8) .................... 54
dsPIC30F4013 Register Map (Bits 7-0) ...................... 54
and Bus Arbitration ............................................. 94
Master Mode ..................................................... 195
Slave Mode ....................................................... 197
Master Mode ..................................................... 196
Slave Mode ....................................................... 198
Master Mode ..................................................... 195
Slave Mode ....................................................... 197
IDLE
) ............................................................ 167
Advance Information
Instruction Addressing Modes ............................................ 35
Instruction Set
Internal Clock Timing Examples ....................................... 177
Interrupt Controller
Interrupt Priority .................................................................. 56
Interrupt Sequence ............................................................. 59
Interrupts ............................................................................ 55
L
Load Conditions................................................................ 175
Low Voltage Detect (LVD) ................................................ 145
Low-Voltage Detect Characteristics.................................. 172
LVDL Characteristics ........................................................ 173
M
Memory Organization ......................................................... 23
Modes of Operation
Modulo Addressing ............................................................. 36
MPLAB ASM30 Assembler, Linker, Librarian ................... 158
MPLAB ICD 2 In-Circuit Debugger ................................... 159
MPLAB ICE 2000 High-Performance Universal
MPLAB ICE 4000 High-Performance Universal
MPLAB Integrated Development Environment
MPLINK Object Linker/MPLIB Object Librarian ................ 158
N
NVM
O
OC/PWM Module Timing Characteristics ......................... 186
Operating Current (I
Operating Frequency vs Voltage
Oscillator
dsPIC30F3014/4013
File Register Instructions ............................................ 35
Fundamental Modes Supported ................................. 35
MAC Instructions ........................................................ 36
MCU Instructions ........................................................ 35
Move and Accumulator Instructions ........................... 36
Other Instructions ....................................................... 36
Overview................................................................... 152
Summary .................................................................. 149
Register Map .............................................................. 62
Traps .......................................................................... 58
Interrupt Stack Frame................................................. 59
Core Register Map ..................................................... 32
Disable...................................................................... 107
Initialization............................................................... 107
Listen All Messages.................................................. 107
Listen Only................................................................ 107
Loopback .................................................................. 107
Normal Operation ..................................................... 107
Applicability................................................................. 38
Incrementing Buffer Operation Example .................... 37
Start and End Address ............................................... 37
W Address Register Selection.................................... 37
In-Circuit Emulator.................................................... 159
In-Circuit Emulator.................................................... 159
Software ................................................................... 157
Register Map .............................................................. 45
dsPIC30FXXXX-20 (Extended) ................................ 163
Configurations .......................................................... 134
Fail-Safe Clock Monitor .................................... 136
Fast RC (FRC).................................................. 135
Initial Clock Source Selection ........................... 134
Low Power RC (LPRC)..................................... 135
LP Oscillator Control......................................... 135
DD
) .................................................... 165
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