ATMEGA88-20MU Atmel, ATMEGA88-20MU Datasheet - Page 152

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ATMEGA88-20MU

Manufacturer Part Number
ATMEGA88-20MU
Description
IC AVR MCU 8K 20MHZ 5V 32-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA88-20MU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Package
32MLF EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
23
Interface Type
SPI/TWI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Processor Series
ATMEGA8x
Core
AVR8
Data Ram Size
1 KB
Maximum Clock Frequency
20 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRTS2080A, ATASTK512-EK1-IND
Minimum Operating Temperature
- 40 C
A/d Inputs
8-Channel, 10-Bit
Cpu Speed
20 MIPS
Eeprom Memory
512 Bytes
Input Output
23
Interface
SPI/TWI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
32-pin MLF
Programmable Memory
8K Bytes
Timers
2-8-bit, 1-16-bit
Voltage, Range
4.5-5.5 V
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
No. Of Timers
3
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
17.11 Register Description
17.11.1
152
ATmega48/88/168
TCCR2A – Timer/Counter Control Register A
The clock source for Timer/Counter2 is named clk
system I/O clock clk
clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter
(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can
then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock
source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal.
For Timer/Counter2, the possible prescaled selections are: clk
clk
Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a
predictable prescaler.
• Bits 7:6 – COM2A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0
bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin
must be set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM22:0 bit setting.
are set to a normal or CTC mode (non-PWM).
Table 17-2.
Table 17-3 on page 153
to fast PWM mode.
Bit
(0xB0)
Read/Write
Initial Value
T2S
COM2A1
/128, clk
0
0
1
1
T2S
Compare Output Mode, non-PWM Mode
COM2A1
R/W
/256, and clk
COM2A0
7
0
0
1
0
1
IO
Table 17-2
. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously
COM2A0
shows the COM2A1:0 bit functionality when the WGM21:0 bits are set
R/W
6
0
Description
Normal port operation, OC2A disconnected.
Toggle OC2A on Compare Match
Clear OC2A on Compare Match
Set OC2A on Compare Match
T2S
/1024. Additionally, clk
shows the COM2A1:0 bit functionality when the WGM22:0 bits
COM2B1
R/W
5
0
COM2B0
R/W
4
0
T2S
. clk
R
3
0
T2S
T2S
as well as 0 (stop) may be selected.
is by default connected to the main
R
2
0
T2S
WGM21
/8, clk
R/W
1
0
T2S
WGM20
R/W
/32, clk
0
0
2545S–AVR–07/10
TCCR2A
T2S
/64,

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