ATMEGA645-16MI Atmel, ATMEGA645-16MI Datasheet - Page 179
![IC AVR MCU FLASH 64K 5V 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA645-16MI
Manufacturer Part Number
ATMEGA645-16MI
Description
IC AVR MCU FLASH 64K 5V 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA325-16MU.pdf
(362 pages)
Specifications of ATMEGA645-16MI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Table 19-7.
1.
19.11 Register Description
19.11.1
2570M–AVR–04/11
Baud
Rate
(bps)
2400
4800
9600
14.4k
19.2k
28.8k
38.4k
57.6k
76.8k
115.2k
230.4k
250k
0.5M
1M
Max.
(1)
UBRR = 0, Error = 0.0%
UDRn – USART I/O Data Register n
UBRR
416
207
103
68
51
34
25
16
12
8
3
3
1
0
U2Xn = 0
Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)
1 Mbps
f
osc
Error
-0.1%
-0.8%
-3.5%
0.2%
0.2%
0.6%
0.2%
0.2%
2.1%
0.2%
8.5%
0.0%
0.0%
0.0%
= 16.0000 MHz
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the
same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Reg-
ister (TXB) will be the destination for data written to the UDRn Register location. Reading the
UDRn Register location will return the contents of the Receive Data Buffer Register (RXB).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to
zero by the Receiver.
The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register is set.
Data written to UDRn when the UDREn Flag is not set, will be ignored by the USART Transmit-
ter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter
will load the data into the Transmit Shift Register when the Shift Register is empty. Then the
data will be serially transmitted on the TxD pin.
Bit
Read/Write
Initial Value
UBRR
832
416
207
138
103
68
51
34
25
16
8
7
3
1
U2Xn = 1
2 Mbps
Error
-0.1%
-0.1%
-0.8%
-3.5%
0.0%
0.2%
0.2%
0.6%
0.2%
0.2%
2.1%
0.0%
0.0%
0.0%
R/W
7
0
UBRR
R/W
479
239
119
6
0
79
59
39
29
19
14
9
4
4
–
–
1.152 Mbps
U2Xn = 0
R/W
f
osc
Error
5
0
-7.8%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
–
–
= 18.4320 MHz
R/W
4
0
RXB[7:0]
TXB[7:0]
UBRR
959
479
239
159
119
79
59
39
29
19
2.304 Mbps
9
8
4
–
U2Xn = 1
ATmega325/3250/645/6450
R/W
3
0
Error
-7.8%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
2.4%
–
R/W
2
0
UBRR
520
259
129
86
64
42
32
21
15
10
R/W
4
4
–
–
1.25 Mbps
1
0
U2Xn = 0
f
osc
Error
-0.2%
-1.4%
-1.4%
-1.4%
R/W
0.0%
0.2%
0.2%
0.2%
0.9%
1.7%
8.5%
0.0%
0
0
–
–
= 20.0000 MHz
UDRn (Write)
UDRn (Read)
UBRR
1041
173
129
520
259
86
64
42
32
21
10
9
4
–
U2Xn = 1
2.5 Mbps
Error
-0.2%
-1.4%
-0.2%
-1.4%
-1.4%
0.0%
0.0%
0.2%
0.2%
0.2%
0.9%
0.0%
0.0%
–
179
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