ATMEGA645-16MI Atmel, ATMEGA645-16MI Datasheet - Page 60
![IC AVR MCU FLASH 64K 5V 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA645-16MI
Manufacturer Part Number
ATMEGA645-16MI
Description
IC AVR MCU FLASH 64K 5V 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA325-16MU.pdf
(362 pages)
Specifications of ATMEGA645-16MI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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13. I/O-Ports
13.1
2570M–AVR–04/11
Overview
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.
This means that the direction of one port pin can be changed without unintentionally changing
the direction of any other pin with the SBI and CBI instructions. The same applies when chang-
ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as
input). Each output buffer has symmetrical drive characteristics with both high sink and source
capability. Port B has a higher pin driver strength than the other ports, but all the pin drivers are
strong enough to drive LED displays directly. All port pins have individually selectable pull-up
resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both
V
a complete list of parameters. If exceeding the pin voltage “Absolute Maximum Ratings”, result-
ing currents can harm the device if not limited accordingly. For segment pins used as general
I/O, the same situation can also influence the LCD voltage level.
Figure 13-1. I/O Pin Equivalent Schematic
All registers and bit references in this section are written in general form. A lower case “x” repre-
sents the numbering letter for the port, and a lower case “n” represents the bit number. However,
when using the register or bit defines in a program, the precise form must be used. For example,
PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis-
ters and bit locations are listed in
Three I/O memory address locations are allocated for each port, one each for the Data Register
– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins
I/O location is read only, while the Data Register and the Data Direction Register are read/write.
However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-
ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the
pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in
61. Most port pins are multiplexed with alternate functions for the peripheral features on the
device. How each alternate function interferes with the port pin is described in
CC
and Ground as indicated in
Pxn
Figure
“Register Description” on page
C
pin
13-1. Refer to
ATmega325/3250/645/6450
“Electrical Characteristics” on page 297
“Ports as General Digital I/O” on page
"General Digital I/O" for
81.
See Figure
R
Details
pu
Logic
“Alternate Port
for
60
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