ATMEGA324P-15MZ Atmel, ATMEGA324P-15MZ Datasheet - Page 361
![MCU AVR 32K FLASH 15MHZ 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA324P-15MZ
Manufacturer Part Number
ATMEGA324P-15MZ
Description
MCU AVR 32K FLASH 15MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA324P-15MZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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7674F–AVR–09/09
BRVC
BRIE
BRID
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
LSL
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
LD
LD
LD
LD
LD
LDD
LD
LD
LD
LDD
LDS
ST
ST
ST
ST
ST
ST
STD
ST
ST
ST
STD
STS
LPM
LPM
LPM
SPM
IN
OUT
Mnemonics
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
s
Rr, b
Rd, b
Rd, Rr
Rd, Rr
Rd, K
Rd, X
Rd, X+
Rd, - X
Rd, Y
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
X, Rr
X+, Rr
- X, Rr
Y, Rr
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Rd, Z
Rd, Z+
Rd, P
P, Rr
k
k
k
Operands
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
Logical Shift Right
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
Move Between Registers
Copy Register Word
Load Immediate
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
Out Port
Description
if (V = 0) then PC
if ( I = 1) then PC
if ( I = 0) then PC
I/O(P,b)
I/O(P,b)
Rd(n+1)
Rd(n)
Rd(0) C,Rd(n+1) Rd(n),C Rd(7)
Rd(7) C,Rd(n) Rd(n+1),C Rd(0)
Rd(n)
Rd(3..0) Rd(7..4),Rd(7..4) Rd(3..0)
SREG(s)
SREG(s)
T
Rd(b)
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
Rd
Rd+1:Rd
Rd
Rd
Rd
X
Rd
Rd
Y
Rd
Rd
Rd
Z
Rd
Rd
(X)
(X)
X
(Y)
(Y)
Y
(Y + q)
(Z)
(Z)
Z
(Z + q)
(k)
R0
Rd
Rd
(Z)
Rd
P
1
0
Rr(b)
1
0
1
0
Z - 1, Rd
Z - 1, (Z)
1
0
1
0
1
0
1
0
1
0
X - 1, Rd
Y - 1, Rd
X - 1, (X)
Y - 1, (Y)
Rr
Rr
Rr
(X)
(X), X
(Y)
(Y), Y
(Y + q)
(Z)
(Z), Z
(Z + q)
Rr
Rr, Y
Rr
Rr, Z
(Z)
(Z)
(Z), Z
R1:R0
P
Rr
Rr, X
K
(k)
Rd(n+1), Rd(7)
Rd(n+1), n=0..6
T
ATmega164P/324P/644P
Rr
Rr
1
0
Rd(n), Rd(0)
Rr+1:Rr
1
0
Z + 1
X + 1
Y + 1
Z+1
Z+1
X + 1
Y + 1
Rr
(Z)
(X)
(Y)
Rr
Rr
Operation
PC + k + 1
PC + k + 1
PC + k + 1
0
0
None
None
None
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Flags
#Clocks
1/2
1/2
1/2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
1
1
-
361
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