SX18AC/SO Parallax Inc, SX18AC/SO Datasheet - Page 30

• Manufacturer Part Number: SX18AC/SO
• Description: IC MCU 2K FLASH 50MHZ SO-18
• Manufacturer: Parallax Inc
• Series: SXr

Specifications of SX18AC/SO

• Core Processor: RISC
• Core Size: 8-Bit
• Speed: 50MHz
• Number Of I /o: 12
• Program Memory Size: 3KB (2K x 12)
• Program Memory Type: FLASH
• Ram Size: 137 x 8
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-SOIC
• Voltage - Supply (vcc/vdd): -
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Connectivity: -

SX18AC / SX20AC / SX28AC
15.12.2 Pop Operation
When a return instruction is executed the subroutine
stack is popped. Specifically, the contents of Stack 1 are
copied into the program counter and the contents of each
stack level are moved to the next higher level. For exam-
ple, Stack 1 receives the contents of Stack 2, etc., until
Stack 7 is overwritten with the contents of Stack 8. Stack
8 is left unchanged, so the contents of Stack 8 are dupli-
cated in Stack 7.
15.13 Comparison and Conditional Branch
The instruction set includes instructions such as DECSZ
fr (decrement file register and skip if zero), INCSZ fr
(increment file register and skip if zero), SNB bit (bit test
file register and skip if bit clear), and SB bit (bit test file
register and skip if bit set). These instructions will cause
the next instruction to be skipped if the tested condition is
true.
15.14 Logical Instruction
The instruction set contain a full complement of the logi-
cal instructions (AND, OR, Exclusive OR), with the W
register and a selected memory location (using either
direct or indirect addressing) serving as the two oper-
ands.
15.15 Shift and Rotate Instructions
The instruction set includes instructions for left or right
rotate-through-carry.
15.16 Complement and SWAP
The device can perform one’s complement operation on
the file register (fr) and W register. The MOV W,<>fr
instruction performs nibble-swap on the fr and puts the
value into the W register.
© 1998 Scenix Semiconductor, Inc. All rights reserved.
Instructions
PC<10:0>
STACK 1
STACK 2
STACK 3
STACK 4
STACK 5
STACK 6
STACK 7
STACK 8
- 30 -
15.17 Key to Abbreviations and Symbols
PA2:PA0 Page select bits in STATUS register (bits 7:5)
STATUS STATUS register (file register 03h)
OPTION OPTION register (not memory-mapped)
Symbol
addr12 12-bit address in assembly language instruc-
MODE
addr8
addr9
WDT
FSR
DC
PC
PD
TO
<>
<<
>>
++
W
rx
- -
C
lit
fr
Z
&
k
n
b
#
^
!
f
.
/
|
Working register
File register (memory-mapped register in the
range of 00h to FFh)
Lower eight bits of program counter (file regis-
ter 02h)
File Select Register (file register 04h)
Carry flag in STATUS register (bit 0)
Digit Carry flag in STATUS register (bit 1)
Zero flag in STATUS register (bit 2
Power Down flag in STATUS register (bit 3)
Watchdog Timeout flag in STATUS register
(bit 4)
Watchdog Timer register (not memory-
mapped)
MODE register (not memory-mapped)
Port control register pointer (RA, RB, or RC)
Non-memory-mapped register designator
File register address bit in opcode
Constant value bit in opcode
Numerical value bit in opcode
Bit position selector bit in opcode
File register / bit selector separator in assem-
bly language instruction
Immediate literal designator in assembly lan-
guage instruction
Literal value in assembly language instruction
8-bit address in assembly language instruction
9-bit address in assembly language instruction
tion
Logical 1’s complement
Logical OR
Logical exclusive OR
Logical AND
Swap high and low nibbles (4-bit segments)
Rotate left through carry flag
Rotate right through carry flag
Decrement file register
Increment file register
Description
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