SX18AC/SO Parallax Inc, SX18AC/SO Datasheet - Page 6

• Manufacturer Part Number: SX18AC/SO
• Description: IC MCU 2K FLASH 50MHZ SO-18
• Manufacturer: Parallax Inc
• Series: SXr

Specifications of SX18AC/SO

• Core Processor: RISC
• Core Size: 8-Bit
• Speed: 50MHz
• Number Of I /o: 12
• Program Memory Size: 3KB (2K x 12)
• Program Memory Type: FLASH
• Ram Size: 137 x 8
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-SOIC
• Voltage - Supply (vcc/vdd): -
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Connectivity: -

SX18AC / SX20AC / SX28AC
3.0 PORT DESCRIPTIONS
The device contains a 4-bit I/O port (Port A) and two 8-bit
I/O ports (Port B, Port C). Port A provides symmetrical
drive capability. Each port has three associated 8-bit reg-
isters (Direction, Data, TTL/CMOS Select, and Pull-Up
Enable) to configure each port pin as Hi-Z input or output,
to select TTL or CMOS voltage levels, and to enable/dis-
able the weak pull-up resistor. The upper four bits of the
registers associated with Port A are not used. The least
significant bit of the registers corresponds to the least
significant port pin. To access these registers, an appro-
priate value must be written into the MODE register.
Upon power-up, all bits in these registers are initialized to
“1”.
The associated registers allow for each port bit to be indi-
vidually configured under software control as shown
below:
© 1998 Scenix Semiconductor, Inc. All rights reserved.
Data Direction
Registers:
RA, RB, RC
Output
0
Input
Hi-Z
Table 3-1. Port Configuration
1
TTL/CMOS
Select Registers:
LVL_A, LVL_B,
LVL_C
CMOS
0
TTL
1
WR
WR
WR
WR
0 = Pullup Enable
1 = Pullup Disable
Pullup Enable
Registers:
PLP_A, PLP_B,
PLP_C
Enable Disable
RD
0 = CMOS
1 = TTL
0 = Output
1 = Hi-Z Input
RA Data
Figure 3-1. Port A Configuration
0
PLP_A
LV_A
Direction
RA
Port A INPUT
1
- 6 -
Port B and Port C have additional associated registers
(Schmitt-Trigger Enable Registers ST_B and ST_C) to
enable or disable the Schmitt Trigger function on each
individual port pin as indicated in table below.
Port B also supports the on-chip differential comparator.
Ports RB1 and RB2 are the comparator negative and
positive inputs, respectively, while Port RB0 is the com-
parator output pin. Port B also supports the Multi-Input
Wakeup feature on all eight pins.
Figure 3-1 shows the internal hardware structure and
configuration registers for each pin of Port A. Figure 3-2
shows the same for each pin of Port B or Port C.
MODE
Schmitt Trigger Enable Registers: ST_B, ST_C
M
U
X
CMOS Buffer
TTL Buffer
Table 3-2. Schmitt Trigger Select
Enable
0
V
dd
Port A PIN
Pullup
(
~
20k )
Disable
1
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