CY8C25122-24PI Cypress Semiconductor Corp, CY8C25122-24PI Datasheet - Page 122
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CY8C25122-24PI
Manufacturer Part Number
CY8C25122-24PI
Description
IC MCU 4K FLASH 256B 8-DIP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ CY8C25xxxr
Datasheet
1.CY8C25122-24PI.pdf
(148 pages)
Specifications of CY8C25122-24PI
Core Processor
M8C
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.25 V
Data Converters
A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Applications
CapSense
Technology
CMOS
Processing Unit
Microcontroller
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Package Type
PDIP
Screening Level
Industrial
Pin Count
8
Mounting
Through Hole
Rad Hardened
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
428-1424
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY8C25122-24PI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
11.10.2.6
The device checksum is retrieved from the device and
compared to the “Device Checksum” from the user’s file
(Note that this is NOT the same thing as the “Record
Checksum.”) The checksum is retrieved from the device
with the following sequence:
CHECKSUM-SETUP(max_data_block)
WAIT-AND-POLL
READ-CHECKSUM(data)
11.11 Programming Wave Forms
Notes :
11.12 Programming File Format
The programming file is created by PSoC Designer, the
Cypress MicroSystems development tool. This tool gen-
erates the programming file in an Intel Hex format.
The programmer should assume the data is 30h/HALT if
it is not specified in the user’s data file.
122
SDATA
1
2
3
SCLK
Vcc
Vcc is only turned off (0V) at the very beginning and the very end of the flow - not within the programming flow.
When the programmer puts the driver on SDATA in a High Z (floating) state, the SDATA pin will float to a low
due to an internal device pull down circuit.
SCLK is set to VILP during the power up and power down; at other times the SCLK is “free running.” The fre-
quency of the hardware’s SCLK signal must be known by the software because the value (entered in the num-
ber of MegaHertz multiplied by the number 5) must be passed into the device with the SET-CLK-FREQ()
mnemonic.
Device Checksum (at Low Vcc and High Vcc)
OUT
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
OUT
Figure 33: Programming Wave Forms
IN
Tssclk
Thsclk
Note : This should be done 2 times; once at Vcc=Vcchv
and once at Vcc=Vcclv.
11.10.2.7
The last step is to power down the device. This is
accomplished by the following sequence:
Set SDATA=HighZ (float pin P1[0])
Set SCLK=0V (Vin on pin P1[1]=Vilp)
Set Vcc = 0V
Power Down
IN
September 5, 2002