CY8C25122-24PI Cypress Semiconductor Corp, CY8C25122-24PI Datasheet - Page 89
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CY8C25122-24PI
Manufacturer Part Number
CY8C25122-24PI
Description
IC MCU 4K FLASH 256B 8-DIP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ CY8C25xxxr
Datasheet
1.CY8C25122-24PI.pdf
(148 pages)
Specifications of CY8C25122-24PI
Core Processor
M8C
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.25 V
Data Converters
A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Applications
CapSense
Technology
CMOS
Processing Unit
Microcontroller
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Package Type
PDIP
Screening Level
Industrial
Pin Count
8
Mounting
Through Hole
Rad Hardened
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
428-1424
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY8C25122-24PI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Analog PSoC Blocks
10.9.3.3
Analog Switch Cap Type A Block xx Control 2 Register
AnalogBus gates the output to the analog column bus.
The output on the analog column bus is affected by the
state of the ClockPhase bit in Control 0 Register
(ASA10CR0, ASA12CR0, ASA21CR0, ASA23CR0). If
AnalogBus is set to 0, the output to the analog column
bus is tri-stated. If AnalogBus is set to 1, the signal that is
output to the analog column bus is selected by the
ClockPhase bit. If the ClockPhase bit is 0, the block out-
put is gated by sampling clock on last part of PHI2. If the
ClockPhase bit is 1, the block output continuously drives
the analog column bus.
CompBus controls the output to the column comparator
bus. Note that if the comparator bus is not driven by any-
thing in the column, it is pulled low. The comparator out-
put is evaluated on the rising edge of internal PHI1 and
is latched so it is available during internal PHI2.
AutoZero controls the shorting of the output to the invert-
ing input of the op-amp. When shorted, the op-amp is
basically a follower. The output is the op-amp offset. By
using the feedback capacitor of the integrator, the block
can memorize the offset and create an offset cancella-
tion scheme. AutoZero also controls a pair of switches
between the A and B branches and the summing node of
the op-amp. If AutoZero is enabled, then the pair of
switches is active. AutoZero also affects the function of
the FSW1 bit in Control 3 Register.
The CCap bits set the value of the capacitor in the C
path.
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
89