CY8C26643-24PI Cypress Semiconductor Corp, CY8C26643-24PI Datasheet - Page 99

• Manufacturer Part Number: CY8C26643-24PI
• Description: IC MCU 16K FLASH 256B 48-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C26xxxr

Specifications of CY8C26643-24PI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-DIP (0.600", 15.24mm)
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: CapSense
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Package Type: PDIP
• Screening Level: Industrial
• Pin Count: 48
• Mounting: Through Hole
• Rad Hardened: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1432; 428-1432-5; 428-1432

10.11 Analog Comparator Bus
Each analog column has a dedicated comparator bus
associated with it. Every analog PSoC block has a com-
parator output that can drive out on this bus, but the
comparator output from only one analog block in a col-
umn can be actively driving the comparator bus for that
column at any one time. The output on the comparator
bus can drive into the digital blocks, and is also available
to be read in the Analog Comparator Control Register
(CMP_CR, Address = Bank 0,64H).
The comparator bus is latched before it is available to
either drive the digital blocks, or be read in the Analog
Comparator Control Register. The latch for each compar-
ator bus is transparent (the output tracks the input) dur-
ing the high period of PHI2. During the low period of
PHI2 the latch retains the value on the comparator bus
during the high to low transition of PHI2.
Table 76:
Analog Comparator Control Register (CMP_CR, Address = Bank 0, 64h)
10.12 Analog Synchronization
For high precision analog operation, it may be necessary
to precisely time when updated register values are avail-
able to the analog PSOC blocks. The optimum time to
update values in Switch Cap registers is at the beginning
of the PHI1 active period. The SYNCEN bit in the Analog
Synchronization Control Register is designed to address
this. (The AINT bits of the Analog Comparator Register
September 5, 2002
Bit 7: COMP 3 COMP 3 bit [0] indicates the state of the analog comparator bus for the Analog Column x
Bit 6: COMP 2 COMP 2 bit [0] indicates the state of the analog comparator bus for the Analog Column x
Bit 5: COMP 1 COMP 1 bit [0] indicates the state of the analog comparator bus for the Analog Column x
Bit 4: COMP 0 COMP 0 bit [0] indicates the state of the analog comparator bus for the Analog Column x
Bit 3: AINT 3 AINT 3 bit [0] or [1] (as defined below) selects the Analog Interrupt Source for the Analog Column x
Bit 2: AINT 2 AINT 2 bit [0] or [1] (as defined below) selects the Analog Interrupt Source for the Analog Column x
Bit 1: AINT 1 AINT 1 bit [0] or [1] (as defined below) selects the Analog Interrupt Source for the Analog Column x
Bit 0: AINT 0 AINT 0 bit [0] or [1] (as defined below) selects the Analog Interrupt Source for the Analog Column x
0 = Comparator bus
1 = PHI2 (Falling edge of PHI2 causes an interrupt)
Bit Name
Read/
Write
Bit #
POR
Analog Comparator Control Register
COMP 3
R
7
0
COMP 2
R
6
0
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
COMP 1
R
5
0
COMP 0
R
4
0
The output from the analog block that is actively driving
the bus may also be latched internal to the analog block
itself.
In the Continuous Time analog blocks, the CPhase and
CLatch bits inside the Analog Continuous Time Type A
Block xx Control Register 2 determine whether the out-
put signal on the comparator bus is latched inside the
block, and if it is, which clock phase it is latched on.
In the Switched Capacitor analog blocks, the output on
the comparator bus is always latched. The ClockPhase
bit in the Analog SwitchCap Type A Block xx Control
Register 0 or the Analog SwitchCap Type B Block xx
Control Register 0 determines the phase on which this
data is latched and available.
(CMP_CR) are another way to address it with interrupts.)
When the SYNCEN bit is set, a subsequent write instruc-
tion to any register in a Switch Cap block will cause the
CPU to stall until the rising edge of PHI1. This mode is in
effect until the SYNCEN bit is cleared.
AINT 3
RW
3
0
AINT 2
RW
2
0
AINT 1
RW
1
0
Analog PSoC Blocks
AINT 0
RW
0
0
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