ST72T141K2M6 STMicroelectronics, ST72T141K2M6 Datasheet
ST72T141K2M6
Specifications of ST72T141K2M6
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ST72T141K2M6 Summary of contents
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Features Memories ■ – 8K Program memory (ROM/OTP) – 256 Bytes RAM Clock, Reset and Supply Management ■ – Enhanced reset system – Low voltage supply supervisor – 3 Power saving modes 14 I/O Ports ■ – 14 multifunctional bidirectional ...
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GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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GENERAL TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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GENERAL DESCRIPTION 1.1 INTRODUCTION The ST72141K devices are members of the ST7 microcontroller family designed specifically for mo- tor control applications and including A/D conver- sion and SPI interface capabilities. They include an on-chip Moter Controller peripheral for control ...
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ST72141K2 1.2 PIN DESCRIPTION Figure 3. 34-Pin SO Package Pinout EXTCLK_B/ (HS) PB1 EXTCLK_A/ (HS) PB0 Figure 4. 32-Pin SDIP Package Pinout EXTCLK_B/ (HS) PB1 EXTCLK_A/ (HS) PB0 6/133 MCO5 1 MCO4 2 MCO3 3 MCO2 4 MCO1 5 MCO0 ...
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PIN DESCRIPTION (Cont’d) Legend / Abbreviations: Type input output supply Input level Dedicated analog input In/Output level CMOS 0. CMOS 0.3V T Output level high sink ...
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ST72141K2 Pin n° Pin Name 20 21 PA3/OCMP2_B/AIN3 I PA4/OCMP1_B/AIN4 I PA5/ICAP2_A/AIN5 I PA6/ICAP1_A/AIN6 I PA7/OCMP2_A/AIN7 I OCMP1_A ...
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EXTERNAL CONNECTIONS The following figure shows the recommended ex- ternal connections for the device. The V pin is only used for programming OTP de- PP vices and must be tied to ground in user mode. The 10 nF and ...
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ST72141K2 1.4 REGISTER & MEMORY MAP As shown in Figure 6, the MCU is capable of ad- dressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 256 bytes of RAM ...
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Table 4. Hardware Register Map Register Address Block Label 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h 0004h PBDR 0005h Port B PBDDR 0006h PBOR 0007h to 001F 0020h MISCR 0021h SPIDR 0022h SPI SPICR 0023h SPISR 0024h WDGCR ...
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ST72141K2 Register Address Block Label 0041h TBCR2 0042h TBCR1 0043h TBSR 0044h TBIC1HR 0045h TBIC1LR 0046h TBOC1HR 0047h TBOC1LR 0048h TIMER B TBCHR 0049h TBCLR 004Ah TBACHR 004Bh TBACLR 004Ch TBIC2HR 004Dh TBIC2LR 004Eh TBOC2HR 004Fh TBOC2LR 0050h to 005Fh ...
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... OTP PROGRAM MEMORY The program memory of the OTP devices can be programmed with EPROM programming tools available from STMicroelectronics. ST72141K2 13/133 ...
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ST72141K2 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 MAIN FEATURES 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ 17 main addressing ...
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CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This ...
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ST72141K2 CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 7Fh SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next ...
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SUPPLY, RESET AND CLOCK MANAGEMENT The ST72141K includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. An overview is ...
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ST72141K2 3.1 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detec- tor function (LVD) generates a static reset when the V supply voltage is below value. This ...
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RESET MANAGER The RESET block includes three RESET sources as shown in Figure 11: External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET ■ Figure 11. Reset Block Diagram V DD RESET The ...
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ST72141K2 RESET MANAGER (Cont’d) External RESET pin The RESET pin is both an input and an open-drain output with integrated R weak pull-up resistor ON (see Figure 11). This pull-up has no fixed value but varies in accordance with the ...
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RESET MANAGER (Cont’d) Internal Low Voltage Detection RESET (option) Two different RESET sequences caused by the in- ternal LVD circuitry can be distinguished: - LVD Power-On RESET - Voltage Drop RESET Figure 13. LVD RESET Sequences DDnominal ...
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ST72141K2 RESET MANAGER (Cont’d) Internal Watchdog RESET The RESET sequence generated by a internal Watchdog counter overflow has the shortest reset phase (see Figure 14). Figure 14. Watchdog RESET Sequence DDnominal V LVDf RUN 22/133 RESET INTERNAL ...
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LOW CONSUMPTION OSCILLATOR The main clock of the ST7 can be generated by two different sources: an external source ■ a crystal or ceramic resonator oscillators ■ External Clock Source In this mode, a square clock signal with ~50% ...
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ST72141K2 3.4 MAIN CLOCK CONTROLLER (MCC) The MCC block supplies the clock for the ST7 CPU and its internal peripherals. It allows the SLOW power saving mode and the Motor Contral and SPI peripheral clocks to be managed inde- pendently. ...
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INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in The ...
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ST72141K2 INTERRUPTS (Cont’d) Figure 18. Interrupt Processing Flowchart FROM RESET EXECUTE INSTRUCTION 26/133 N I BIT SET? Y FETCH NEXT INSTRUCTION N IRET? Y LOAD PC FROM INTERRUPT VECTOR RESTORE PC FROM STACK THIS CLEARS I BIT ...
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INTERRUPTS (Cont’d) Table 5. Interrupt Mapping Source N° Block RESET Reset TRAP Software Interrupt 0 Not used 1 EI0 External Interrupt Port A7..0 (C5..0*) 2 EI1 External Interrupt Port B7..0 (C5..0*) 3 Motor Control Interrupt (events MTC ...
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ST72141K2 5 POWER SAVING MODES 5.1 Introduction To give a large measure of flexibility to the applica- tion in terms of power consumption, three main power saving modes are implemented in the ST7 (see Figure 19). After a RESET the ...
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POWER SAVING MODES (Cont’d) 5.2 HALT Mode The HALT mode is the lowest power consumption mode of the MCU entered by executing the ST7 HALT instruction (see Figure The MCU can exit HALT mode on reception of ei- ...
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ST72141K2 POWER SAVING MODES (Cont’d) 5.3 WAIT Mode WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the “WFI” ST7 software instruction. All peripherals remain ...
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I/O PORTS 6.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ripherals. An I/O ...
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ST72141K2 I/O PORTS (Cont’d) Figure 23. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS ALTERNATE ENABLE DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT SOURCE ( POLARITY SELECTION Table 6. ...
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I/O PORTS (Cont’d) Table 7. I/O Port Configurations NOT IMPLEMENTED TRUE OPEN DRAIN I/O PORTS R PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V DD I/O PORTS R PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V DD ...
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ST72141K2 I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as ...
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I/O PORTS (Cont’d) Interrupt Ports PA7:0, PB5:3 (with pull-up) MODE floating input pull-up interrupt input open drain output push-pull output True Open Drain Interrupt Ports PB2:0 (without pull-up) MODE floating input floating interrupt input true open drain (high sink ports) ...
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ST72141K2 I/O PORTS (Cont’d) 6.3.1 Register Description DATA REGISTER (DR) Port x Data Register PxDR with Read/Write Reset Value: 0000 0000 (00h Bit 7:0 = D[7:0] Data register 8 ...
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I/O PORTS (Cont’d) Table 9. I/O Port Register Map and Reset Values Address Register 7 Label (Hex.) Reset Value 0 of all IO port registers 0000h PADR 0001h PADDR MSB 0002h PAOR 0004h PBDR 0005h PBDDR MSB 0006h PBOR 6 ...
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ST72141K2 7 MISCELLANEOUS REGISTER The miscellaneous register allows control over several different features such as the external in- terrupts or the I/O alternate functions. 7.1 I/O Port Interrupt Sensitivity Description The external interrupt sensitivity is controlled by the ISxx bits ...
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MISCELLANEOUS REGISTER (Cont’d) 7.4 Miscellaneous Register Description MISCELLANEOUS REGISTER (MISCR) Read/Write Reset Value: 0000 0000 (00h) 7 XT16 SSM SSI IS11 IS10 Bit 7 = XT16 MTC and SPI clock selection This bit is set and cleared by software. The ...
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ST72141K2 8 ON-CHIP PERIPHERALS 8.1 MOTOR CONTROLLER (MTC) 8.1.1 Introduction The ST7 Motor Controller (MTC) can be seen as a Pulse Width Modulator multiplexed on six output channels, and a Back Electromotive Force (BEMF) zero-crossing detector for sensorless con- trol ...
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MOTOR CONTROLLER (Cont’d) The MTC manages these three events always in the same order: Z generates C after a delay com- puted in realtime, then waits for D in order to ena- ble the peripheral to detect another Z event. ...
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ST72141K2 MOTOR CONTROLLER (Cont’d) Figure 27. Example of Command Sequence for 6-step Mode (typical 3-phase PMDC Motor Control) Step 1 2 Switch Node HV/2 C ...
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MOTOR CONTROLLER (Cont’d) Table 12. Step Configuration Summary Configuration Current direction High side Low side OO[5:0] bits in MPHST register Measurement done on: IS[1:0] bits in MPHST register Back EMF shape CPB bit in MCRB register (ZVD bit = 0) ...
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ST72141K2 MOTOR CONTROLLER (Cont’d) 8.1.4 Functional Description The MTC can be split into four main parts as shown in the simplified block diagram in – The BEMF ZERO-CROSSING DETECTOR with a comparator and an input multiplexer. – The DELAY MANAGER ...
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MOTOR CONTROLLER (Cont’d) Input Pins The MCIA, MCIB and MCIC input pins can be used as analog pins in Sensorless mode or as dig- ital pins in Sensor mode. In sensorless mode, the analog inputs are used to measure the ...
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ST72141K2 MOTOR CONTROLLER (Cont’d) Sensorless Mode This mode is used to detect BEMF zero crossing and end of demagnetization events. The analog phase multiplexer connects the non- excited motor winding to an analog 100mV hyster- esis comparator referred to a ...
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MOTOR CONTROLLER (Cont’d) Demagnetization (D) Event At the end of the demagnetization phase, current no longer goes through the free-wheeling diodes. The voltage on the non-excited winding terminal goes from one of the power rail voltages to the common star ...
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ST72141K2 MOTOR CONTROLLER (Cont’d) Table 14. Demagnetisation (D) Event Generation (example for ZVD=0) HDM Meaning bit motor parasite or first HVV Software Mode 0 (SDM bit =1 and HDM bit = 0) HV/2 0V motor parasite or first HV Hardware/Simulat- ...
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MOTOR CONTROLLER (Cont’d) BEMF Zero Crossing (Z) Event When both C and D events have occurred, the PWM may be switched to another group of outputs (depending on the OS[2:0] bits in the MCRB regis- ter) and the real BEMF ...
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ST72141K2 MOTOR CONTROLLER (Cont’d) Sensor Mode In sensor mode, the rotor position information is given to the peripheral by means of logical data on the three inputs MCIA, MCIB and MCIC. For each step one of these three inputs is ...
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MOTOR CONTROLLER (Cont’d) Figure 32. Functional Diagram of Z Detection after D Event Switch Sampling Clock[D] -> Sampling Clock[ Begin 20 s Filter turned on No Side change on Output PWM ? Yes Change the ...
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ST72141K2 MOTOR CONTROLLER (Cont’d) Table 16. Modes permitting BEMF reading after Demagnetization (D event) SR bit V0C1 bit Demagnet- (Sensor/ (Voltage/ ization Sensor- Current less Mode) Mode) 1 After D 0 event Not Used x Other cases ...
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MOTOR CONTROLLER (Cont’d) 8.1.4.2 Delay Manager Figure 33. Overview of MTIM Timer Z § MZREG [ § MZPRV [Z ] n-1 § MCOMP [C ] n+1 § = Register updated on R event This part of the ...
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ST72141K2 MOTOR CONTROLLER (Cont’d) At this time all registers with a preload function are loaded (registers marked with (*) in Section 8.1.7). The CI bit of MISR is set and if the CIM bit in the MISR register is set ...
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MOTOR CONTROLLER (Cont’d) Figure 34. Step Ratio Functional Diagram MPRSR Register MTIM Timer control over T MTIM Timer Overflow Begin Ratio < Fh? Yes Ratio = Ratio + Zn+1 = Zn+1 Dn/2 ...
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ST72141K2 MOTOR CONTROLLER (Cont’d) Autoswitched Mode In this mode the MCOMP register content is auto- matically computed in real time as described be- low and in Figure 35. This register is READ ONLY. The C event has no effect on ...
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MOTOR CONTROLLER (Cont’d) Table 20. MTIM Timer-related Registers Name Reset Value MTIM 00h MZPRV 00h MZREG 00h MCOMP 00h MDREG 00h Demagnetization Dn Note on using the auto-updated MTIM timer: The auto-updated MTIM timer works accurately within its operating range ...
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ST72141K2 MOTOR CONTROLLER (Cont’d) The Figure 36 gives the step ratio register value (left axis) and the number of BEMF sampling dur- ing one electrical step with the corresponding ac- curacy on the measure (right axis function of ...
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MOTOR CONTROLLER (Cont’d) Table 21. Step Frequency/Period Range Step Ratio Bits Maximum ST[3:0] Step Frequency 0000 23.5 kHz 0001 11.7 kHz 0010 5.88 kHz 0011 2.94 kHz 0100 1.47 kHz 0101 735 Hz 0110 367 Hz 0111 183 Hz 1000 ...
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ST72141K2 MOTOR CONTROLLER (Cont’d) 8.1.4.3 PWM Manager The PWM manager controls the motor via the six output channels in voltage mode or current mode depending on the V0C1 bit in the MCRA register. A block diagram of this part is ...
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MOTOR CONTROLLER (Cont’d) The measurement window frequency can be pro- grammed between 195Hz and 25KHz by the means of the SA[3:0] bits in the MPRSR register. In sensorless mode this measurement window can be used to detect either End of ...
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ST72141K2 MOTOR CONTROLLER (Cont’d) 8.1.4.4 Channel Manager The channel manager consists of: – A Phase State register with preload and polarity function – A multiplexer to direct the PWM to the odd and/ or even channel group – A tristate ...
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MOTOR CONTROLLER (Cont’d) Direct access to the phase register is also possible when the DAC bit in the MCRA register is set. Table 26. DAC and MOE Bit Meaning Effect on MOE bit DAC bit Output 0 x High Z ...
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ST72141K2 MOTOR CONTROLLER (Cont’d) Figure 40. Step Behaviour of one Output Channel MCO[n] in Voltage Mode OS2 PWM behaviour before D 0 Not Alternate 1 Alternate Even 000 1 Odd 0 Even 001 1 Odd 0 Even ...
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MOTOR CONTROLLER (Cont’d) Figure 41. Step Behaviour of one Output Channel MCO[n] in Current / Sensorless Mode (Current Mode without polarity effect, sensorless mode: SR=0) OS2 PWM behaviour before Even Channels 1 On Odd Channels Demagnetization 1 ...
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ST72141K2 MOTOR CONTROLLER (Cont’d) 8.1.5 Low Power Modes Before executing a HALT or WFI instruction, soft- ware must stop the motor, and may choose to put the outputs in high impedance. Mode Description No effect on MTC interface. WAIT MTC ...
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MOTOR CONTROLLER (Cont’d) 8.1.7 Register Description TIMER COUNTER REGISTER (MTIM) Read/Write Reset Value: 0000 0000 (00h Bits 7:0 = T[7:0]: MTIM Counter Value. These bits contain the current value of the 8-bit up counter. ...
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ST72141K2 MOTOR CONTROLLER (Cont’d) INTERRUPT MASK REGISTER (MIMR) Read/Write (except bits 7:6) Reset Value: 0000 0000 (00h) 7 HST CL RIM OIM EIM Bit 7 = HST: Hysteresis Comparator Value. This read only bit contains the hysteresis compa- rator output. ...
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MOTOR CONTROLLER (Cont’d) Table 28. Step Ratio Update Ratio MOE SWA Clock Read Increment bit bit State (Slow Down) Disa- Write the ST[3:0] value di bled rectly in the MPRSR register Al- Set RPI bit in Ena- ways ...
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ST72141K2 MOTOR CONTROLLER (Cont’d) Table 32. Multiplier Result DCB bit Commutation Delay 0 MCOMP = MWGHT x MZPRV / 32 1 MCOMP = MWGHT x MZREG / 32 CONTROL REGISTER B (MCRB) Read/Write Reset Value: 0000 0000 (00h) 7 VR1 ...
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MOTOR CONTROLLER (Cont’d) PHASE STATE REGISTER (MPHST) Read/Write Reset Value: 0000 0000 (00h) 7 IS1* IS0* OO5* OO4* OO3* Bits 7:6 = IS[1:0]*: Input Selection bits These bits select the input to connect to compara- tor as shown in the ...
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ST72141K2 MOTOR CONTROLLER (Cont’d) Note: The CPB, HDM, SDM, OS2 bits in the MCRB and the bits OE[5:0] are marked with *. It means that these bits are taken into account at the following commutation event (in normal mode) or ...
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MOTOR CONTROLLER (Cont’d) Figure 43. Detailed view of the MTC Reg MPHST ST72141K2 bit MOE Reg MPOL Reg MPAR bit CFF Reg MIMR Reg MISR 73/133 ...
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ST72141K2 MOTOR CONTROLLER (Cont’d) Table 38. MTC Register Map and Reset Values Address Register 7 Name (Hex.) MTIM T7 0060h Reset Value 0 MZPRV ZP7 0061h Reset Value 0 MZREG ZC7 0062h Reset Value 0 MCOMP DC7 0063h Reset Value ...
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WATCHDOG TIMER (WDG) 8.2.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its ...
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ST72141K2 WATCHDOG TIMER (Cont’d) 8.2.3 Functional Description The counter value stored in the CR register (bits T6:T0), is decremented every 12288 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. ...
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WATCHDOG TIMER (Cond’t) Table 40. Watchdog Timer Register Map and Reset Values Address Register 7 (Hex.) Label WDGCR WDGA 0024h Reset Value 0 WDGSR - 0025h Reset Value ...
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ST72141K2 8.3 16-BIT TIMER 8.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths two input sig- nals ...
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TIMER (Cont’d) Figure 45. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 OCF2 ICIE OCIE TOIE FOLV2 FOLV1 (Control Register 1) ...
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ST72141K2 16-BIT TIMER (Cont’d) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Returns the buffered Read Byte value at ...
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TIMER (Cont’d) Figure 46. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 47. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER ...
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ST72141K2 16-BIT TIMER (Cont’d) 8.3.3.3 Input Capture In this section, the index, i, may because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used ...
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TIMER (Cont’d) Figure 49. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 50. Input Capture Timing Diagram TIMER CLOCK FF01 COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER ...
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ST72141K2 16-BIT TIMER (Cont’d) 8.3.3.4 Output Compare In this section, the index, i, may because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or ...
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TIMER (Cont’d) Notes: 1. After a processor write cycle to the OCiHR reg- ister, the output compare function is inhibited until the OCiLR register is also written the OCiE bit is not set, the OCMPi pin is ...
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ST72141K2 16-BIT TIMER (Cont’d) Figure 52. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) Figure 53. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER ...
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TIMER (Cont’d) 8.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input ...
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ST72141K2 16-BIT TIMER (Cont’d) Figure 54. One Pulse Mode Timing Example FFFC FFFD FFFE COUNTER ICAP1 OCMP1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 55. Pulse Width Modulation Mode Timing Example FFFC FFFD FFFE COUNTER 34E2 OCMP1 compare2 Note: OC1R=2ED0h, OC2R=34E2, ...
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TIMER (Cont’d) 8.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode ...
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ST72141K2 16-BIT TIMER (Cont’d) 8.3.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode ...
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TIMER (Cont’d) 8.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ...
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ST72141K2 16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the ...
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TIMER (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 Bit 7 = ICF1 Input Capture Flag input capture (reset ...
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ST72141K2 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 HIGH (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE 2 ...
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TIMER (Cont’d) Table 42. 16-Bit Timer Register Map and Reset Values Address Register 7 (Hex.) Label Timer A: 32 CR1 ICIE Timer B: 42 Reset Value 0 Timer A: 31 CR2 OC1E Timer B: 41 Reset Value 0 Timer ...
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ST72141K2 8.4 SERIAL PERIPHERAL INTERFACE (SPI) 8.4.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 57. Serial Peripheral Interface Block Diagram Read Read Buffer MOSI MISO 8-Bit Shift Register Write SCK SS Internal Bus DR SPIF WCOL SPIE SPE SPR2 MSTR MASTER CONTROL SERIAL CLOCK GENERATOR ST72141K2 IT request SR ...
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ST72141K2 SERIAL PERIPHERAL INTERFACE (Cont’d) 8.4.4 Functional Description Figure 56 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: – A Control Register (CR) – A Status Register (SR) – A Data Register (DR) Refer ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 8.4.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure – ...
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ST72141K2 SERIAL PERIPHERAL INTERFACE (Cont’d) 8.4.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to syn- chronize the data transfer during a sequence of ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 59. Data Clock Timing Diagram SCLK (with CPOL = 1) SCLK (with CPOL = 0) MSBit MISO (from master) MSBit MOSI (from slave) SS (to slave) CAPTURE STROBE CPOL = 1 CPOL = 0 MSBit ...
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ST72141K2 SERIAL PERIPHERAL INTERFACE (Cont’d) 8.4.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is tak- ing place with an external device. When this hap- pens, the ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 8.4.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: – ...
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ST72141K2 SERIAL PERIPHERAL INTERFACE (Cont’d) 8.4.4.7 Single Master and Multimaster Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured, using an MCU as ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 8.4.5 Low Power Modes Mode No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. HALT In HALT mode, the SPI is inactive. SPI operation resumes ...
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ST72141K2 SERIAL PERIPHERAL INTERFACE (Cont’d) 8.4.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by software. 0: Interrupt ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) 7 SPIF WCOL - MODF - Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been ...
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ST72141K2 SERIAL PERIPHERAL INTERFACE (Cont’d) Table 44. SPI Register Map and Reset Values Address Register 7 (Hex.) Label SPIDR MSB 0021h Reset Value x SPICR SPIE 0022h Reset Value 0 SPISR SPIF 0023h Reset Value 0 108/133 ...
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A/D CONVERTER (ADC) 8.5.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer ...
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ST72141K2 8-BIT A/D CONVERTER (ADC) (Cont’d) 8.5.3 Functional Description The high level reference voltage V connected externally to the V DD reference voltage V must be connected exter- SSA nally to the V pin. In some devices (refer to de- ...
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A/D CONVERTER (ADC) (Cont’d) 8.5.6 Register Description CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) 7 COCO - ADON 0 - Bit 7 = COCO Conversion Complete This bit is set by hardware cleared by soft- ...
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ST72141K2 9 INSTRUCTION SET 9.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld ...
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ST7 ADDRESSING MODES (Cont’d) 9.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait For ...
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ST72141K2 ST7 ADDRESSING MODES (Cont’d) 9.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index ...
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INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and ...
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ST72141K2 INSTRUCTION GROUPS (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) ...
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INSTRUCTION GROUPS (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset carry ...
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ST72141K2 10 ELECTRICAL CHARACTERISTICS 10.1 ABSOLUTE MAXIMUM RATINGS This product contains devices for protecting the in- puts against damage due to high static voltages, however it is advisable to take normal precautions to avoid applying any voltage higher than the ...
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RECOMMENDED OPERATING CONDITIONS GENERAL Symbol Parameter V Supply voltage DD Resonator oscillator frequency f OSC External clock source T Ambient temperature range A 10.3 DC ELECTRICAL CHARACTERISTICS Recommended operating conditions with T Symbol Parameter Supply current in RUN mode ...
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ST72141K2 10.5 I/O PORT CHARACTERISTICS Recommended operating conditions o with T =-40 to +125 C and 4.5V<V A I/O PORT PINS Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis ...
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SUPPLY, RESET AND CLOCK CHARACTERISTICS 10.6.1 Supply Manager Recommended operating conditions with T LOW VOLTAGE DETECTOR (LVD) Symbol Parameter V Reset release threshold LVDr V Reset generation threshold LVDf Hysteresis LVDhyst LVD rise ...
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ST72141K2 10.7 PERIPHERAL CHARACTERISTICS WATCHDOG Symbol Parameter t Watchdog time-out duration w(WDG) t Watchdog RESET pulse width WDGRST Recommended operating conditions with T MOTOR CONTROL Symbol Parameter V Comparator offset error OFFSET V MCIA/B/C comparator hysteresis MTChyst t Comparator propagation ...
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MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d) SPI Serial Peripheral Interface Ref. Symbol Parameter f SPI frequency SPI 1 t SPI clock period SPI 2 t Enable lead time Lead 3 t Enable lag time Lag 4 t Clock (SCK) high time ...
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ST72141K2 MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d) Figure 66. SPI Master Timing Diagram CPHA=0, CPOL=1 SS (INPUT) SCK (OUTPUT) MISO (INPUT) 6 MOSI (OUTPUT) 10 Figure 67. SPI Master Timing Diagram CPHA=1, CPOL=0 SS (INPUT) SCK (OUTPUT) 4 MISO (INPUT) 6 ...
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MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d) Measurement points are Figure 69. SPI Slave Timing Diagram CPHA=0, CPOL=0 SS (INPUT) 2 SCK (INPUT) 4 MISO HIGH-Z D7-OUT (OUTPUT) 8 MOSI D7-IN (INPUT) 6 Figure 70. SPI Slave Timing ...
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ST72141K2 MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d) ADC Analog to Digital Converter (8-bit) Symbol Parameter 3) |TUE| Total unadjusted error 3) OE Offset error 3) GE Gain Error |DLE| Differential linearity error 3) |ILE| Integral linearity error V Conversion range voltage ...
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MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d) R AIN V AIN Px.x/AINx C = input capacitance pin V = threshold voltage sampling switch C = sample/hold hold capacitance leakage = leakage current at the pin due to various junctions ...
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ST72141K2 11 PACKAGE CHARACTERISTICS In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level in- terconnect. The category of second Level Inter- connect is marked on the package and on ...
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Figure 74. 34-Pin Plastic Small Outline Package, Shrink 300-mil Width Dim 45× Note 1. Values in inches are converted from mm and rounded to 4 decimal digits. ST72141K2 ...
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... TEMP. DEVICE PACKAGE RANGE 130/133 The selected options are communicated to STMi- croelectronics using the correctly completed OP- TION LIST appended. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points. / XXX Code name (defined by STMicroelectronics) 6= -40 to +85 °C 3= -40 to +125 °C ...
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... Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phone Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STMicroelectronics references Device ST72141K2 Package SO34 Conditioning Tube [ ] Tape & Reel (not available for SDIP packages) Temperature Range -40 to 85° ...
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ST72141K2 12 SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one. Rev. Added VtPOR in section 10.6.1 on page 121 1.8 Modified VMTChyst and Voffset in Modified Option list in Section ...
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... ST and the ST logo are trademarks or registered trademarks various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - ...